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7133LA70GB Datasheet, PDF (10/16 Pages) Integrated Device Technology – HIGH SPEED 2K X 16 DUAL-PORT SRAM
◁
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(6)
7133X20
7143X20
Com'l Only
7133X25
7143X25
Com'l, Ind
& Military
7133X35
7143X35
Com'l, Ind
& Military
Symbol
BUSY TIMING (For MASTER 71V33)
Parameter
tBAA
BUSY Access Time from Address
tBDA
BUSY Disable Time from Address
tBAC
BUSY Access Time from Chip Enable
tBDC
BUSY Disable Time from Chip Enable
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
tBDD
BUSY Disable to Valid Data(2)
tAPS
Arbitration Priority Set-up Time(3)
tWH
Write Hold After BUSY(5)
BUSY INPUT TIMING (For SLAVE 71V43)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
Min. Max. Min. Max. Min. Max. Unit
____
20
____
20
____
30
ns
____
20
____
20
____
30
ns
____
20
____
20
____
25
ns
____
17
____
20
____
25
ns
____
40
____
50
____
60
ns
____
30
____
35
____
45
ns
____
25
____
30
____
35
ns
5
____
5
____
5
____
ns
20
____
20
____
25
____
ns
0
____
20
____
____
40
____
30
7133X45
7143X45
Com'l &
Military
0
____
20
____
____
50
____
35
7133X55
7143X55
Com'l, Ind
& Military
0
____
25
____
____
60
____
45
7133X70/90
7143X70/90
Com'l &
Military
ns
ns
ns
ns
2746 tbl 12a
Symbol
BUSY TIMING (For MASTER 71V33)
Parameter
tBAA
BUSY Access Time from Address
tBDA
BUSY Disable Time from Address
tBAC
BUSY Access Time from Chip Enable
tBDC
BUSY Disable Time from Chip Enable
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
tBDD
BUSY Disable to Valid Data(2)
tAPS
Arbitration Priority Set-up Time(3)
tWH
Write Hold After BUSY(5)
BUSY INPUT TIMING (For SLAVE 71V43)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
Min. Max. Min. Max. Min. Max. Unit
____
40
____
40
____
45/45 ns
____
40
____
40
____
45/45 ns
____
30
____
35
____
35/35 ns
____
25
____
30
____
30/30 ns
____
80
____
80
____
90/90 ns
____
55
____
55
____
70/70 ns
____
40
____
40
____
40/40 ns
5
____
5
____
5/5
____
ns
30
____
30
____
30/30
____
ns
0
____
0
____
0/0
____
ns
30
____
30
____
30/30
____
ns
____
80
____
80
____
90/90 ns
____
55
____
55
____
70/70 ns
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".
2. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual).
3. To ensure that the earlier of the two ports wins.
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (SA or LA).
2746 tbl 12b
61.402
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