841N4830 Datasheet, PDF (7/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

841N4830 DATA SHEET
Table 6C. HCSL AC Characteristics, V_DD = 3.0V to 3.6V, V_DDO = 2.7V to 3.6V, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
f_OUT
Output Frequency
PLL
PLL Bypass
100
20
f_REF
Reference Frequency
25
tsk(b)
Bank Skew; NOTE 1, 10
tjit(Ø)
Phase Jitter, RMS (Random); 100MHz, Integration Range:
NOTE 11
12kHz – 20MHz
t_{REFCLK_HF_RMS} Phase Jitter RMS; NOTE 2
100MHz, 25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.600
t_{REFCLK_LF_RMS} Phase Jitter RMS; NOTE 2
100MHz, 25MHz crystal input
Low Band: 10kHz - 1.5MHz
0.023
tjit(cc)
Cycle-to-Cycle Jitter
PLL Mode
t_L
PLL Lock Time
V_RB
Ring-back Voltage Margin;
NOTE 4, 9
-100
t_STABLE
Time before V_RB is allowed;
NOTE 4, 9
500
V_HIGH
V_LOW
V_CROSS
Voltage High
Voltage Low
Absolute Crossing Voltage;
NOTE 3, 6, 7
520
-150
160
V_CROSS
Total Variation of V_CROSS
over all edges; NOTE 3, 6, 8
Rising Edge Rate; NOTE 4, 5
0.6
Falling Edge Rate; NOTE 4, 5
0.6
PSNR
Power Supply Noise
Reduction
-45
odc
Output Duty Cycle; NOTE 4
49
Maximum
50
0.36
Units
MHz
MHz
MHz
ps
ps
ps
ps
30
ps
10
ms
100
mV
ps
920
mV
150
mV
460
mV
140
mV
4.0
V/ns
4.0
V/ns
dB
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}
(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 3: Measurement taken from single ended waveform.
NOTE 4: Measurement taken from differential waveform.
NOTE 5: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 6: Measured at the crosspoint where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
NOTE 7: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoints
for this measurement.
NOTE 8: Defined as the total variation of all crossing voltages of rising Q and falling nQ, This is the maximum allowed variance in V_CROSS for
any particular system.
NOTE 9: T_STABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V_RB ±100mV differential range.
NOTE 10: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 11: See Phase Noise Plot.
Rev E 7/1/15
7
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER