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| 841N4830 Datasheet, PDF (20/28 Pages) Integrated Device Technology – Fourth generation FemtoClock | |||
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841N4830 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 841N4830.
Equations and example calculations are also provided.
1. Power Dissipation
The total power dissipation for the 841N4830 is the sum of the core power plus the power dissipated due to loading. The following is the power
dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3A and 3B for details on calculating power dissipation due to loading.
Core
⢠Power(core) = VDD_MAX * IEE = 3.6V * 170mA = 612mW
LVPECL Output
LVPECL driver power dissipation is 30mW/Loaded output pair, total LVPECL output dissipation:
⢠Power(LVPECL) = 30mW
HSCL Output
HSCL driver power dissipation is 46.8mW/Loaded output pair, total HSCL output dissipation:
⢠Power(HSCL) = 46.75mW * 3 = 140.25mW
LVCMOS Output
⢠Output Impedance ROUT Power Dissipation due to Loading 50ï to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50ï + ROUT)] = 3.6V / [2 * (50ï + 25ï)] = 24mA
⢠Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 25ï * (24mA)2 = 14.4mW per output
⢠Total Power Dissipation on the ROUT
Total Power (ROUT) = 14.4mW * 2 = 28.8mW
Dynamic Power Dissipation at 100MHz
Power (100MHz) = CPD * Frequency * (VDD)2 = 5pF * 100MHz * (3.6V)2 = 6.48mW per output
Total Power (100MHz) = 6.48mW * 2 = 12.96mW
Total Power Dissipation
⢠Total Power
= Power (core) + Power(LVPECL) + Power(HCSL) + Total Power (ROUT) + Total Power (100MHz)
= 612mW + 30mW + 140.25mW + 28.8mW +12.96mW
= 824mW
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER
20
Rev E 7/1/15
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