841N4830 Datasheet, PDF (17/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

841N4830 DATA SHEET
Schematic Example
Figure 8 shows an example of 841N4830 application schematic. The
schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
In this example, the device is operated at V_DD = V_{DDO_REF} =
V_{DD_OSC} = V_DDO = 3.3V. The 12pF parallel resonant 25MHz crystal
is used. The C1 = 5pF and C2 = 5pF are recommended for frequency
accuracy. For different board layouts, the C1 and C2 may be slightly
adjusted for optimizing frequency accuracy. When designing the
circuit board, return the capacitors to ground though a single point
contact close to the package.
Two examples of HCSL terminations are shown in this schematic.
The decoupling capacitors should be located as close as possible to
the power pin.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 841N4830 provides separate
power supplies to isolate any high switching noise from coupling into
the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uf capacitor in each power pin filter should be placed on the device
side. The other components can be on the opposite side of the PCB.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10 kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
Rev E 7/1/15
17
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER