841N4830 Datasheet, PDF (18/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

841N4830 DATA SHEET
3.3 V
FB1
1
2
C14
0. 1uF
BLM18 BB221 SN1
C15
10uF
VD D
VDDO
C8
R6
0. 1uF
10
nOEA
C9
C3
10u
0. 1uF
R8
10
U1
3.3V
FB2
2
1
BLM18 BB221 SN1
C17
10uF
C1 6
0. 1uF
C13
0. 1uF
R3
4 75
Zo = 50 O hm
REF_OUT
TL1
Zo = 50 O hm
nREF_OUT
TL2
LVPECL Termination
3 .3V_Rec eive r
R1
R2
1 33
133
+
R4
8 2.5
-
R5
82.5
C4
10u
Zo =5 0
Zo =5 0
L VPECL Dr ive r
C5
0. 1u
PLL_ BYPASS
nREF_OE
nOEB
QB_DIV2
CLK
nCLK
1
2 ^{PL L_BYPASS}
3 ^{nREF_ OE}
4 ^nOEB
5 ^DIV2_QB
6 ^{VDD A}
7 ^CLK
8 ^nCLK
VDD O_REF
R2 3
50
R14
50
R 22
50
C7
0.1u F
VDDO
C1
5pF
X1
2 5MH₁ z_{2 p F}
Logic Control Input Examples
VDD
Set Logic
Input to '1'
VDD
Set Logic
Input to '0'
XTAL_ IN
XTAL_ OUT
C2
5 pF
24
QA1 ₂₃
n QA1 ₂₂
VDD O ₂₁
QA2 ₂₀
n QA2 ₁₉
GN D ₁₈
QA3 ₁₇
VDDO_ QA3
QB
VDDO
C11
0. 1uF
R2 1
VDD
10
C10
0 .1uF
RU1
1K
To Logic
In pu t
p ins
RD1
Not Ins tall
RU2
Not Ins tall
To Lo gic
In pu t
p ins
RD2
1K
V DD=VD DO=3.3 V
V DDO_R EF= VD D_OSC=3. 3V
V DDO_QA 3=VD DO_QB =3.3 V
VDDO
C12
0. 1uF
VDDO
C6
0. 1uF
R7 33
QA0
R9 33
nQA0
R 10
50
Zo = 50
+
TL3
Zo = 50
-
TL4
R1 1
50
Use for PCI Express
Add-In Card
HCSL Termination
Optional
QA2
R1 6 33
R1 7 33
n QA2
Zo = 50
TL7
Zo = 50
TL8
+
-
R18
R19
50
50
Use for PCI Express
Point-to-Point Connection
R20 2 5
Zo = 50
QB
LVCMOS
Figure 8. 841N4830 Application Schematic
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER
18
Rev E 7/1/15