841N4830 Datasheet, PDF (3/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

841N4830 DATA SHEET
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
R_PULLDOWN
C_PD
R_OUT
Input Pullup Resistors
Input Pulldown Resistors
Power Dissipation
Capacitance (per output)
Output
Impedance
QA3, QB
Test Conditions
CLK, nCLK
Control Pins
V_DD, V_{DD_OSC,} V_DDO, V_{DDO_REF,}
V_{DDO_QA3,} V_{DDO_QB} = 3.6V
V_{DDO_QA3,} V_{DDO_QB} = 3.6V
Minimum
Typical
2
4
100
100
5
25
Maximum
Units
pF
pF
k
k
pF

Function Tables
Table 3A. nOEA Function Table
Input
nOEA
0 (default)
1
Outputs
QA
Active
High-Impedance
Table 3C. nOE_REF Function Table
Input
Outputs
nOE_REF
REF_OUT
0 (default)
Active
1
High-Impedance
Table 3E. CLK_SEL Function Table
Input
CLK_SEL
Selected Input
0
XTAL
1 (default)
CLK, nCLK
Table 3B. nOEB Function Table
Input
nOEB
0 (default)
1
Outputs
QB
Active
High-Impedance
Table 3D. PLL_BYPASS Function Table
Input
Outputs
PLL_BYPASS
QA, QB
0 (default)
PLL
1
Bypass PLL
Table 3F. DIV2_QB Function Table
Input
DIV2_QB
Output Frequency
0
100MHz
1 (default)
50MHz
Rev E 7/1/15
3
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER