841N4830 Datasheet, PDF(15/28 Page) Integrated Device Technology

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841N4830 Datasheet, PDF (15/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

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841N4830 DATA SHEET

Recommendations for Unused Input Pins

Inputs:

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1kï resistor can be tied from CLK to ground.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1kï resistor can be tied from

XTAL_IN to ground.

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1kï resistor can be used.

Outputs:

LVPECL Output

The unused LVPECL output pair can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

LVCMOS Outputs

All unused LVCMOS output can be left floating. There should be no

trace attached.

Differential Outputs

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are recom-

mended only as guidelines.

The differential outputs are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating resis-

tors (DC current path to ground) or current sources must be used for

functionality. These outputs are designed to drive 50ï transmission

lines. Matched impedance techniques should be used to maximize

operating frequency and minimize signal distortion. Figures 6A and

6B show two different layouts which are recommended only as guide-

lines. Other suitable clock layouts may exist and it would be recom-

mended that the board designers simulate to guarantee compatibility

across all printed circuit and clock component process variations.

3.3V

125ï

3.3V

Zo = 50ï

84ï

Input

Figure 6A. 3.3V LVPECL Output Termination

Figure 6B. 3.3V LVPECL Output Termination

Rev E 7/1/15

FEMTOCLOCKÂ® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER

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