841N4830 Datasheet, PDF (22/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

841N4830 DATA SHEET
3A. Calculations and Equations for LVPECL.
The purpose of this section is to calculate power dissipation on the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 9.
V_DDO
Q1
V_OUT
RL
V_DDO - 2V
Figure 9. LVPECL Driver Circuit and Termination
To calculate power dissipation per output due to loading, use the following equations which assume a 50 load, and a termination voltage of
V_DDO – 2V.
• For logic high, V_OUT = V_{OH_MAX} = V_{DDO_MAX} – 0.9V
(V_{CC_MAX} – V_{OH_MAX}) = 0.9V
• For logic low, V_OUT = V_{OL_MAX} = V_{DDO_MAX} – 1.7V
(V_{CC_MAX} – V_{OL_MAX}) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V_{OH_MAX} – (V_{DDO_MAX} – 2V))/R_L] * (V_{DDO_MAX} – V_{OH_MAX}) = [(2V – (V_{DDO_MAX} – V_{OH_MAX}))/R_L] * (V_{DDO_MAX} – V_{OH_MAX}) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V_{OL_MAX} – (V_{DDO_MAX} – 2V))/R_L] * (V_{DDO_MAX} – V_{OL_MAX}) = [(2V – (V_{DDO_MAX} – V_{OL_MAX}))/R_L] * (V_{DDO_MAX} – V_{OL_MAX}) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER
22
Rev E 7/1/15