841N4830 Datasheet, PDF (23/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

3B. Calculations and Equations for HCSL.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pairs.
HCSL output driver circuit and termination are shown in Figure 10.
VDDO
I_OUT = 17mA
841N4830 DATA SHEET
R_REF =
475Ω ± 1%
V_OUT
R_L
50Ω
IC
Figure 10. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when V_DD__MAX.
Power = (V_{DD_MAX} – V_OUT) * I_OUT,
since V_OUT – I_OUT * R_L
= (V_{DD_MAX} – I_OUT * R_L) * I_OUT
= (3.6V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 46.75mW
Rev E 7/1/15
23
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER