841N4830 Datasheet, PDF (12/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

841N4830 DATA SHEET
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 841N4830 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V_DD, V_{DD_OSC,} V_DDA, V_DDO, and V_DDOx should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic V_DD pin and also shows that V_DDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V_DDA pin.
V_DD
VDDA
3.3V
.01µF
10Ω
10Ω
.01µF 10µF
V_DDA
.01µF 10µF
Figure 1. Power Supply Filtering
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential
signals. Both V_SWING and V_OH must meet the V_PP and V_CMR input
requirements. Figures 2A to 2D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for open emitter LVHSTL drivers. If you are using an LVHSTL
driver from another vendor, use their termination recommendation.
3.3V
*R3
*R4
HCSL
3.3V
CLK
nCLK
Differential
Input
Figure 2A. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 2B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER
Figure 2D. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
12
Rev E 7/1/15