841N4830 Datasheet, PDF (13/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

841N4830 DATA SHEET
Crystal Input Interface
The 841N4830 has been characterized with 12pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 25MHz, 12pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
X1
12pF Parallel Crystal
XTAL_IN
C1
5pF
XTAL_OUT
C2
5pF
Figure 3. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be accomplished
by removing R1 and making R2 50. By overdriving the crystal
oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
3.3V
Ro ~ 7 Ohm
RS 43
Driv er_LVCMOS
3.3V
R1
100
Zo = 50 Ohm
R2
100
C1
0.1uF
XTAL_IN
XTAL_OUT
Cry stal Input Interf ace
Figure 4A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
C1
XTAL_IN
R1
0.1uF
50
XTAL_OUT
Cry stal Input Interf ace
R2
50
R3
50
Figure 4B. General Diagram for LVPECL Driver to XTAL Input Interface
Rev E 7/1/15
13
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER