841N4830 Datasheet, PDF (2/28 Pages) Integrated Device Technology – Fourth generation FemtoClock

841N4830 DATA SHEET
Table 1. Pin Descriptions
Number
Name
Type
Description
1
PLL_BYPASS
Input
Pulldown
When HIGH, PLL is bypassed and outputs are driven by input crystal or clock. When
LOW outputs are driven by PLL. LVCMOS/LVTTL interface levels. See Table 3D.
2
nOE_REF
Input
Pulldown
Output enable signal for REF_OUT output. When LOW, outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3C.
3
nOEB
Input
Pulldown
Output enable signal for Bank B. When LOW, QB output is enabled. When HIGH,
selects high impedance mode. LVCMOS/LVTTL interface levels.See Table 3B.
4
DIV2_QB
Input
Pullup
Select signal for the output divider for Bank B. LVCMOS/LVTTL clock output. See
Table 3F.
5, 32
6
V_DDA
CLK
Power
Analog supply pins.
Input Pulldown Non-inverting differential clock input.
7
nCLK
Input Pullup Inverting differential clock input.
8
9, 10
V_{DDO_REF}
REF_OUT,
nREF_OUT
Power
Output
Output power supply pin for LVPECL reference outputs.
25MHz differential reference output pair. LVPECL interface levels.
11
CLK_SEL
Input
Pullup
Input select signal. When HIGH, selects CLK, nCLK inputs. When LOW, selects
XTAL inputs. LVCMOS/LVTTL interface levels.See Table 3E.
12
13
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output.
14
V_{DD_OSC}
Power
15
V_{DDO_QB}
Power
16
QB
Output
Core supply pin for crystal oscillator.
Output power supply pin for Bank B LVCMOS output.
Single-ended output. LVCMOS/LVTTL interface levels.
17
V_{DDO_QA3}
Power
18
QA3
Output
Output power supply pin for QA3 LVCMOS output.
Single-ended output. LVCMOS/LVTTL interface levels.
19, 25
GND
Power
Power supply ground.
20, 21
nQA2, QA2 Output
100MHz differential output pair. HCSL interface levels.
22, 29
23, 24
V_DDO
nQA1, QA1
Power
Output
Output power supply pins for Bank A HCSL outputs.
100MHz differential output pair. HCSL interface levels.
26, 27
nQA0, QA0 Output
100MHz differential output pair. HCSL interface levels.
28
IREF
0.7V current reference resistor output. An external fixed precision resistor (475)
from this pin to ground provides a reference current used for differential
current-mode QAx, nQAx clock outputs.
30
nOEA
Input
Pulldown
Output Enable signal for Bank A. When LOW enables output. When HIGH selects
high impedance mode. LVCMOS/LVTTL interface levels.See Table 3A.
31
V_DD
Power
Core supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
FEMTOCLOCK® NG CRYSTAL-TO-HCSL FREQUENCY SYNTHESIZER
2
Rev E 7/1/15