90E36 Datasheet, PDF (6/79 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

List of Figures
Figure-1 90E36 Block Diagram .................................................................................................................................................................................... 8
Figure-2 Pin Assignment (Top View) ............................................................................................................................................................................ 9
Figure-3 Energy Register Operation Diagram ............................................................................................................................................................ 14
Figure-4 CFx Pulse Output Regulation ...................................................................................................................................................................... 15
Figure-5 Metering Startup Handling ........................................................................................................................................................................... 16
Figure-6 Analysis Function ......................................................................................................................................................................................... 19
Figure-7 Block Diagram in Normal Mode ................................................................................................................................................................... 20
Figure-8 Block Diagram in Idle Mode ......................................................................................................................................................................... 21
Figure-9 Block Diagram in Detection Mode ................................................................................................................................................................ 23
Figure-10 Block Diagram in Partial Measurement mode ............................................................................................................................................. 24
Figure-11 Power Mode Transition ............................................................................................................................................................................... 25
Figure-12 Slave Mode ................................................................................................................................................................................................. 27
Figure-13 Master Mode (PIN_DIR_SEL=0) ................................................................................................................................................................. 27
Figure-14 Read Sequence ........................................................................................................................................................................................... 28
Figure-15 Write Sequence ........................................................................................................................................................................................... 28
Figure-16 Clock Mode0 (CLK_DRV=0, CLK_IDLE=0) and Mode1 (CLK_DRV=0, CLK_IDLE=1) .............................................................................. 29
Figure-17 Clock Mode2 (CLK_DRV=1, CLK_IDLE=0) and Mode3 (CLK_DRV=1, CLK_IDLE=1) .............................................................................. 30
Figure-18 Sample Sequence Example ........................................................................................................................................................................ 30
Figure-19 Sample Bit Sequence Example ................................................................................................................................................................... 31
Figure-20 IRQ and WarnOut Generation ..................................................................................................................................................................... 41
Figure-21 Current Detection Register Latching Scheme ............................................................................................................................................. 49
Figure-22 Start and Checksum Register Operation Scheme ...................................................................................................................................... 54
Figure-23 SPI Timing Diagram .................................................................................................................................................................................... 72
Figure-24 DMA Timing Diagram .................................................................................................................................................................................. 73
Figure-25 Power On Reset Timing (90E36 and MCU are Powered on Simultaneously) ............................................................................................ 74
Figure-26 Power On Reset Timing in Normal & Partial Measurement Mode .............................................................................................................. 74
Figure-27 Zero-Crossing Timing Diagram (per phase) ................................................................................................................................................ 75
Figure-28 Voltage Sag and Phase Loss Timing Diagram ............................................................................................................................................ 76
List of Figures
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December 9, 2011