90E36 Datasheet, PDF (31/79 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

90E36
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Samples
Samples on MOSI
CS
I1 I2 V3
b23
b16 b15
b8 b7
b0 0 0 0 0 0 0 0 0
8 pads
I1 sample N
Figure-19 Sample Bit Sequence Example
4.3.2 CONTROL SEQUENCE FOR EXTERNAL DEVICE
To start and stop the DMA dump sequence, the external device fol-
lows the rules described below:
• Start of the dump process:
a) The external device configures the DMACtrl register.
b) The external device switches to SPI slave mode. Note that the
parameters of clock idle state / driving edge, sample bit width and pin
direction of SPI_D0/SPI_D1 configured to 90E36 should match with
external device's settings.
c) The external device asserts the DMA_CTRL signal. The 90E36
swaps I/O direction if necessary after it has detected that master has
asserted the DMA. The samples are dumped out with a delay of at most
1 sample period (125us).
• Stop of the dump process:
a) The external device de-asserts the DMA_CTRL signal. The 90E36
stops the transaction after current (all selected) samples have been suc-
cessfully sent out.
b) The external device waits one sample period of 125us or detects
that the CS signal is pulled high, then switches the interface back to
master mode.
SPI / DMA Interface
31
December 9, 2011