90E36 Datasheet, PDF (48/79 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

90E36
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
DMACtrl
DMA Mode Interface Control
Address: 0EH
Type: Read/Write
Default Value: 7E44H
Bit
Name
Description
These bits configure the data source of the ADC channel. Each bit enables the data dumping for one ADC channel as the follow-
ing diagram shows. Set a ‘1’ to a bit enables the dumping of the corresponding ADC channel samples.
15:9
ADC_CH_SEL
b15 b14 b13 b12 b11 b10 b9
I4
I1
V1
I2
V2
I3
V3
Note: I1 to phase A and I3 to phase C mapping can be swapped by configuring the I1I3Swap bit (b13, MMode0).
This bit configures the direction of the SDI and SDO pins.
8
PIN_DIR_SEL
PIN_DIR_SEL
0
1
Master Mode
(DMA_Ctrl=1)
SDI→MOSI
SDO←MISO
SDI←MISO
SDO→MOSI
These bits configure the bit width for each channel.
7:6
CH_BIT_WIDTH
Code
00
01
10
11
Channel Bit Width
32 bits
24 bits (default)
16 bits
reserved
This bit configures the Idle state clock level.
5
CLK_IDLE 0: Idle low (default)
1: Idle High
This bit configures which edge to drive data out.
4
CLK_DRV 0: Second edge drives data out. (default)
1: First edge drives data out.
3:0
CLK_DIV Divide ratio to generate SCLK frequency from SYS_CLK. Default value is ‘100’.
6.2.4 LAST SPI DATA REGISTER
LastSPIData
Last Read/Write SPI Value
Address: 0FH
Type: Read
Default Value: 0000H
Bit
Name
Description
15:0
LastSPIData15 - This register is a special register which logs data of the previous SPI Read or Write access especially for Read/Clear registers.
LastSPIData0 This register is useful when the user wants to check the integrity of the last SPI access.
Register
48
December 9, 2011