90E36 Datasheet, PDF (30/79 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

90E36
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
CLOCK Cycle #
SCLK
(CLK_IDLE=0)
SCLK
(CLK_IDLE=1)
SDI/SDO
1234
N-2 N-1 N
CS
Figure-17 Clock Mode2 (CLK_DRV=1, CLK_IDLE=0) and Mode3 (CLK_DRV=1, CLK_IDLE=1)
For mode0 and mode1 (CLK_DRV = 0), the first edge of SCLK is ADC Channel Selection. During CS de-asserted state, the SCLK stays
used by the slave to sample the data.
in idle state as configured by the CLK_IDLE bit (b5, DMACtrl).
For mode2 and mode3 (CLK_DRV=1), the first edge of SCLK is used
by the master to drive out the data.
CS Deactivation for Rate Adaptation
Data Frame Format and Sample Sequence in DMA Mode
The 90E36 sends the ADC samples (In 8K sample rate) continuously
in DMA mode.
Since the bit rate may be higher than the equivalent bit rate of the
samples (For example, for 24-bit non-frame mode, the equivalent bit-
rate is sample_rate*6*24bps). To compensate for that, the CS signal is
de-asserted to wait for the new samples and be asserted again once the
new sample arrives.
There are at least 2 SCLK clock periods for CS resume from de-
asserted state to assert state depending on the Clock Dividing Ratio and
The samples of all enabled ADC channels are sent out in interleaved
manner, with the sequence of I4, I1, V1, I2, V2, and I3, V3 (If any chan-
nel is disabled, remove it from the list while maintaining the sequence of
the other channels). Figure-18 shows an example of the sample
sequence when the ADC_CH_SEL[15:9] bits (b15~9, DMACtrl) are con-
figured to be ‘0101001’.
Samples on
MOSI
CS
I1 I2 V3
I1 I2 V3
I1 I2 V3
Samples 1
Samples 2
Samples N
T=125µs
Figure-18 Sample Sequence Example
Bit Sequence
The samples sent over the interfaces are the processed data accord-
ing to the CH_BITWIDTH[7:6] bits (b7~6, DMACtrl). All the samples sent
are MSB first. Figure-19 shows an example of sample bit sequence for
32-bit sample bit width.
SPI / DMA Interface
30
December 9, 2011