90E36 Datasheet, PDF (29/79 Pages) Integrated Device Technology – Poly-Phase High-Performance Wide-Span Energy Metering IC

90E36
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
4.3 MASTER MODE: DMA
The interface is defined to connect with various DSP processors for
ADC samples dumping.
For DMA configure please refer to DMACtrl register definition in 6.2
Special Registers.
The interface works in Master mode when the DMA_CTRL pin is
pulled high by the external device. In Master mode, registers in 90E36
cannot be accessed. The dump transaction can be stopped by the exter-
nal device via pulling the DMA_CTRL pin to low at any time.
Figure-13 shows a connection between 90E36 and a DSP processor
where 90E36 acts as the master.
4.3.1 DMA BURST TRANSFER FOR ADC SAMPLING
When the DMA_CTRL pin changes from low to high, the voltage and
current channel ADC samples (after decimation and frequency compen-
sation) are dumped out serially through the interface with SCLK fre-
quency defined by the CLK_DIV[3:0] bits (b3~0, DMACtrl).
When the 90E36 detects that the DMA_CTRL pin is de-asserted, it
stops the DMA transaction after the current sample has been sent.
Clock Dividing Ratio
The SCLK frequency of SPI interface is defined by the CLK_DIV[3:0]
bits (b3~0, DMACtrl) as the following equation:
f _SCLK
=
f _{sys_clk}
CLK_DIV * 2 + 2
Here f_{sys_clk} means system’s oscillator frequency.
Interface Direction
In DMA mode, the interface direction of SDI/SDO pins are normally
defined as Figure-13. But the direction also can be swapped by configur-
ing the PIN_DIR_SEL bit (b8, DMACtrl).
ADC Channel Selection
Internally, the 90E36 has 7 ADC channels. The user can select which
channel’s samples to be dumped out via configuring the ADC_CH_SE
L[15:9] bits (b15~9, DMACtrl).
Each bit of the 7-bit field ADC_CH_SEL enables the data dumping
for one ADC channel. Set ‘1’ to a bit enables the dump of the corre-
sponding ADC channel samples.
Clock Modes
Four clock modes are defined in master mode according to the
CLK_DRV bit (b4, DMACtrl) and CLK_IDLE bit (b5, DMACtrl) configura-
tion as the following diagram shows.
CLOCK Cycle #
SCLK
(CLK_IDLE=0)
SCLK
(CLK_IDLE=1)
SDI/SDO
1234
N-2 N-1 N
CS
Figure-16 Clock Mode0 (CLK_DRV=0, CLK_IDLE=0) and Mode1 (CLK_DRV=0, CLK_IDLE=1)
SPI / DMA Interface
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December 9, 2011