ICS8743008I Datasheet, PDF (5/28 Pages) Integrated Device Technology – FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

ICS8743008I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Number
46, 47
48
49
50
51
52
53
54
55
56
Name
nQ0/Q0
QDIV7
QDIV6
QDIV5
QDIV4
V_DDA
CLK
nCLK
PDIV0
PDIV1
Type
Output
Input Pulldown
Input Pulldown
Input Pulldown
Input
Power
Input
Input
Input
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Input Pulldown
Description
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
Output Divider Control for Q7/nQ7. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Output Divider Control for Q6/nQ6. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Output Divider Control for Q5/nQ5. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Output Divider Control for Q4/nQ4. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Analog supply pin.
Non-inverting differential clock input.
Accepts HCSL, LVDS, M-LVDS, HSTL input levels.
Inverting differential clock input.
Accepts HCSL, LVDS, M-LVDS, HSTL input levels.
Input Divide Select 0. Together with PDIV1 determines the input divider
value. LVCMOS/LVTTL Interface levels.
Input Divide Select 1. Together with PDIV0 determines the input divider
value. LVCMOS/LVTTL Interface levels.
NOTE: Pullup and Pulldown refer to intenal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 5
ICS8743008DKI REV. A AUGUST 25, 2008