ICS8743008I Datasheet, PDF (2/28 Pages) Integrated Device Technology – FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

ICS8743008I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Block Diagram
MR¹ (PD)
PDIV1 (PD)
PDIV0 (PD)
CLK (PD)
nCLK (PU/PD)
MR (PD)
OE_MLVDS (PU)
MLVDS
nMLVDS
PDIV1:0
00 ÷4 (default)
01 ÷5
10 ÷8
11 ÷1
FBI_DIV1 (PU)
FBI_DIV0 (PU)
FBIN (PD)
nFBIN (PU/PD)
MR¹ (PD)
PLL_SEL (PU)
MR¹ (PD)
FBI_DIV1:0
00 ÷1
01 ÷2
10 ÷4
11 ÷5 (default)
QDIV0
0 ÷4 (default)
1 ÷5
3
OE2:0 (PU, PU)
QDIV0 (PD)
Q0
nQ0
0
PD
VCO
490-660 MHz ¹
QDIV7
0 ÷4 (default)
1 ÷5
FBO_DIV
0 ÷4 (default)
1 ÷5
8 Differential LVPECL or LVDS Pairs
QDIV7 (PD)
Q7
nQ7
FBO_DIV (PD)
FBOUT
nFBOUT
Q_TYPE (PD)
1_{One master reset pin is used to reset all the internal dividers, but the MR lines are not drawn as all tied together to reduce control line clutter, making the block diagram easier to read}
PU means internal pull-up resistor on pin (power-up default is HIGH if not externally driven)
PD means internal pull-down resistor on pin (power-up default is LOW if not externally driven)
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 2
ICS8743008DKI REV. A AUGUST 25, 2008