ICS8743008I Datasheet, PDF (24/28 Pages) Integrated Device Technology – FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

ICS8743008I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 9.
V_DDO
PRELIMINARY
Q1
V_OUT
RL
50Ω
V_DDO - 2V
Figure 9. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of V_DDO – 2V.
• For logic high, V_OUT = V_{OH_MAX} = V_{DDO_MAX} – 0.9V
(V_{DDO_MAX} – V_{OH_MAX}) = 0.9V
• For logic low, V_OUT = V_{OL_MAX} = V_{DDO_MAX} – 1.7V
(V_{DDO_MAX} – V_{OL_MAX}) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V_{OH_MAX} – (V_{DDO_MAX} – 2V))/R_L] * (V_{DDO_MAX} – V_{OH_MAX}) = [(2V – (V_{DDO_MAX} – V_{OH_MAX}))/R_L] * (V_{DDO_MAX} – V_{OH_MAX}) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V_{OL_MAX} – (V_{DDO_MAX} – 2V))/R_L] * (V_{DDO_MAX} – V_{OL_MAX}) = [(2V – (V_{DDO_MAX} – V_{OL_MAX}))/R_L] * (V_{DDO_MAX} – V_{OL_MAX}) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 24
ICS8743008DKI REV. A AUGUST 25, 2008