ICS8743008I Datasheet, PDF (17/28 Pages) Integrated Device Technology – FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

ICS8743008I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
via external pullup resistor to HIGH state. OE_MLVDS defaults to
Logic 1(active) and this is what we need, so that pin can be left
floating. The FBO_DIV and FB_IN dividers default to the desired
values, so their respective control pins can be left floating
(FBO_DIV and FBI_DIV1:0). QDIV0 needs to be ÷4, which is a
default value so this pin can be left floating. QDIV1 must be HIGH
for ÷5, so this pin must be pulled high or driven high externally.
OE[2:0] = 001, so OE0 can Float and OE[2:1] must be pulled Low
2255MMHHzz
MMLLVVDDSS
MnMLVLVDDS S
MMaasstteerr CClloocckk CCaarrdd
IICCSS88774433000088II
÷÷44
CCLLKK 110000MMHHzzLLVVDDSS
CnLCKLK
SSSSCCSSyynntthheessiizzeerr
IICCSS884411SS3322II
FFeemmttooCClloocckk
VVCCOO
110000 MMHHzz LLVVDDSS
FFPPGGAA
112255 MMHHzz LLVVDDSS
PPCCIIee SSeerrddeess
BBaacckkppllaannee
2255MMHHzz
MMLLVVDDSS
SSllaavvee CClloocckk CCaarrdd
SSllaavvee ssyynntthheessiizzeerr
OOffff oorr oouuttppuutt ddiissaabblleedd
IICCSS88774433000088II
÷÷44
CCLLKK
CnLCKLK
SSSSCC SSyynntthheessiizzeerr
IICCSS884411SS3322II
FFeemmttooCClloocckk
VVCCOO
110000 MMHHzz LLVVDDSS
FFPPGGAA
112255MMHHzzLLVVDDSS
PPCCIIee SSeerrddeess
Figure 1. Example Backplane Application
Bold lines
indicate active clock path
This example shows a case where each card may be dynamically
configured as a master or slave card, hence the need for an
ICS8743008I and ICS841402I on each card. On the master timing
card, the ICS841402I provides a 100MHz reference to the
ICS8743008I CLK/nCLK input. The M-LVDS pair on the
ICS8743008I is configured as an output (OE_MLVDS = Logic 1)
and the internal divider is set to ÷4 to generate 25MHz M-LVDS to
the backplane. The 25MHz clock is also used as a reference to the
FemtoClock PLL which multiplies to a VCO frequency of 500MHz.
Each of the eight output pairs may be individually set for ÷4 or ÷5
for 125MHz or 100MHz operation respectively and in this example,
one output pair is set to 100MHz for the FPGA and another output
pair is set to 125MHz for the PCI Express serdes. For the slave
card, the M-LVDS pair is configured as an input (OE_MLVDS =
LOW) and the FemtoClock PLL multiplies this reference frequency
to 500MHz VCO frequency and the output dividers are set to
provide 100MHz to the FPGA and 125MHz to the PCI Express
Serdes as shown.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 17
ICS8743008DKI REV. A AUGUST 25, 2008