ICS8743008I Datasheet, PDF (4/28 Pages) Integrated Device Technology – FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

ICS8743008I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Number
13
Name
OE2
15
16
17
18
20
21
22
23
24, 25
27, 28
FBI_DIV0
FBI_DIV1
nFBIN
FBIN
QDIV0
QDIV1
QDIV2
QDIV3
Q7/nQ7
Q6/nQ6
29
Q_TYPE
30, 37, 42, 45
31,
32
V_DDO
nFBOUT,
FBOUT
33, 34
nQ5/Q5
35, 36
nQ4/Q4
38, 39
nQ3/Q3
40, 41
nQ2/Q2
43, 44
nQ1/Q1
Continued on next page.
Type
Input
Pullup
Input
Pullup
Input
Input
Input
Pullup
Pullup/
Pulldown
Pulldown
Input Pulldown
Input Pulldown
Input Pulldown
Input Pulldown
Output
Output
Input Pulldown
Power
Output
Output
Output
Output
Output
Output
Description
Output Enable. Together with OE0 and OE1, determines the output state of
the outputs with the default state: all output pairs switching. When an HCSL
output pair is disabled, the disable state is Qx = LOW, nQx = HI-Z. It should
also be noted that the feedback output pins (FBOUT/nFBOUT) are always
switching and are not affected by the state of OE[2:0]. Refer to table 3B for
truth table. LVCMOS/LVTTL Interface levels
Feedback Input Divide Select 0. Together with FB_DIV1, determines the
feedback input divider value. LVCMOS/LVTTL interface levels.
Feedback Input Divide Select 1. Together with FB_DIV0, determines the
feedback input divider value. LVCMOS/LVTTL interface levels.
Inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.”
Output Divider Control for Q0/nQ0. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Output Divider Control for Q1/nQ1. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Output Divider Control for Q2/nQ2. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Output Divider Control for Q3/nQ3. Determines if the output divider = ÷4
(default), or ÷5. LVCMOS/LVTTL interface levels.
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
Output Type Select. 0 = LVDS outputs (default); 1 = LVPECL outputs on
Q0/nQ0:Q7/nQ7, and FBOUT/nFBOUT. The MLVDS/nMLVDS driver is
always M-LVDS and is NOT affected by the state of this pin.
LVCMOS/LVTTL interface levels.
Output supply pins.
Differential feedback output pair.The feedback ouput pair always switches
independent of the output enable settings on the OE[2:0] pins.
LVDS or LVPECL interface levels.
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
Differential LVDS or LVPECL output pair. The output type is controlled by the
Q_TYPE pin as follows: Q_TYPE = 0 LVDS (default); Q_TYPE = 1 LVPECL.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 4
ICS8743008DKI REV. A AUGUST 25, 2008