ICS8743008I Datasheet, PDF (1/28 Pages) Integrated Device Technology – FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

PRELIMINARY
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/
CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET
ICS8743008I
General Description
The ICS8743008I is Zero-Delay Buffer/Frequency
ICS
Multiplier with eight differential LVDS or LVPECL
HiPerClockS™ _{output pairs (pin selectable output type), and uses}
external feedback for “zero delay” clock
regeneration. In PCI Express and Ethernet
applications, 100MHz and 125MHz are the most commonly used
reference clock frequencies and each of the eight output pairs can
be independently set for either 100MHz or 125MHz. With an
output frequency range of 98MHz to 165MHz, the device is also
suitable for use in a variety of other applications such as Fibre
Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS
Input/Output pair is useful in backplane applications when the
reference clock can either be local (on the same board as the
ICS8743008I) or remote via a backplane connector. In output
mode, an input from a local reference clock applied to the
CLK/nCLK input pins is translated to M-LVDS and driven out to the
MLVDS/nMLVDS pins. In input mode, the internal M_LVDS driver
is placed in Hi-Z state using the OE_MLVDS pin and
MLVDS/nMLVDS pin then becomes an input (e.g. from a
backplane).
The ICS8743008I uses very low phase noise FemtoClock
technology, thus making it ideal for such applications as PCI
Express Generation 1 and 2 as well as for Gigabit Ethernet, Fibre
Channel, and 10 Gigabit Ethernet. It is packaged in a 56-VFQFN
package (8mm x 8mm).
Features
• Eight differential output pairs with selectable pin type: LVDS or
LVPECL. Each output pair is individually selectable for 100MHz
or 125MHz (for PCIe and Ethernet applications).
• One differential clock input pair CLK/nCLK can accept the
following differential input levels: LVPECL, LVDS, M-LVDS,
LVHSTL, HCSL
• One M-LVDS I/O (MLVDS/nMLVDS)
• Output frequency range: 98MHz - 165MHz
• Input frequency range: 19.6MHz - 165MHz
• VCO range: 490MHz - 660MHz
• PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
• External feedback for “zero delay” clock regeneration
• RMS phase jitter @ 125MHz (1.875MHz – 20MHz):
0.57ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
Pin Assignment
VDD
OE_MLVDS
MLVDS
nMLVDS
GND
PLL_SEL
V_DD
nc
FBO_DIV
MR
OE0
OE1
OE2
GND
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
42
2
41
3
40
4
39
5
38
6
37
7
36
8
35
9
34
10
33
11
32
12
31
13
30
14
29
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VDDO
Q2
nQ2
Q3
nQ3
VDDO
Q4
nQ4
Q5
nQ5
FBOUT
nFBOUT
V_DDO
Q_TYPE
ICS8743008I
56-Lead VFQFN
8mm x 8mm x 0.925mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 1
ICS8743008DKI REV. A AUGUST 25, 2008