ICS8743008I Datasheet, PDF (21/28 Pages) Integrated Device Technology – FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

ICS8743008I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 6. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
50Ω
LVDS Driver
50Ω
100Ω Differential Transmission Line
Figure 6. Typical LVDS Driver Termination
R1
100Ω
3.3V
+
–
3.3V M-LVDS Driver Termination
A general M-LVDS interface is shown in Figure 7 In a 100Ω
differential transmission line environment, M-LVDS drivers require
a matched load termination of 100Ω across near the receiver input.
For a multiple M-LVDS outputs buffer, if only partial outputs are
used, it is recommended to terminate the unused outputs.
3.3V
LVDS Driver
50Ω
R2
100Ω
50Ω
R1
100Ω
100Ω Differential Transmission Line
Figure 7. Typical M-LVDS Driver Termination
3.3V
+
–
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 21
ICS8743008DKI REV. A AUGUST 25, 2008