ICS8743008I Datasheet, PDF (3/28 Pages) Integrated Device Technology – FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS™ AND ETHERNET

ICS8743008I
FEMTOCLOCKS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 7
Name
V_DD
2
OE_MLVDS
3
MLVDS
4
nMLVDS
5, 14, 19
6
8, 26
9
GND
PLL_SEL
nc
FBO_DIV
10
MR
11
OE0
12
OE1
Continued on next page.
Type
Power
Input
Pullup
I/O
I/O
Power
Input
Pullup
Unused
Input Pulldown
Input Pulldown
Input
Pullup
Input
Pullup
Description
Core supply pins.
Active High Output Enable. When HIGH, the M-LVDS output driver is active
and provides a buffered copy of reference clock applied the CLK/nCLK input
to the MLVDS/nMLVDS output pins. The MLVDS/nMLVDS frequency equals
the CLK/nCLK frequency divided by the PDIV Divider value (selectable ÷1,
÷4, ÷5, ÷8). When LOW, the M-LVDS output driver is placed into a Hi-Z state
and the MLVDS/nMLVDS pins can accept a differential input.
LVCMOS/LVTTL interface levels.
Non-Inverting M-LVDS input/output. The input/output state is determined by
the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and
drives the non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin
is an input and can accept the following differential input levels: M-LVDS,
LVDS, LVPECL, HSTL, HCSL.
Inverting M-LVDS input/output. The input/output state is determined by the
OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives
the inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input
and can accept the following differential input levels: M-LVDS, LVDS,
LVPECL, HSTL, HCSL. The output driver is always M-LVDS and is not
affected by the state of the Q-TYPE pin which affects Q0/nQ0:Q7/nQ7, and
FBOUT/nFBOUT.
Power supply ground.
PLL select. Determines if the PLL is in bypass or enabled mode (default). In
enabled mode, the output frequency = VCO frequency/QDIV divider. In
bypass mode, the output frequency = reference clock frequency/
(PDIV*QDIV). LVCMOS/LVTTL interface levels.
No connect.
Output Divider Control for the feedback output pair, FBOUT/nFBOUT.
Determines if the output divider = ÷4 (default), or ÷5.
LVCMOS/LVTTL interface levels.
Active High master reset. When logic HIGH, the internal dividers are reset
causing the Qx/nQx outputs to drive Hi-Z. Note that assertion of MR overrides
the OE[0:2] control pins and all outputs are disabled. When logic LOW, the
internal dividers are enabled and the state of the outputs is determined by
OE[0:2]. MR must be asserted on power-up to ensure outputs phase aligned.
LVCMOS/LVTTL interface levels.
Output Enable. Together with OE1 and OE2, determines the output state of
the outputs with the default state: all output pairs switching. When an LVDS
or LVPECL output pair is disabled, the disable state is Qx/nQx = Hi-Z. It
should also be noted that the feedback output pins (FBOUT/nFBOUT) are
always switching and are not affected by the state of OE[2:0]. Refer to table
3B for truth table. LVCMOS/LVTTL Interface levels.
Output Enable. Together with OE0 and OE2, determines the output state of
the outputs with the default state: all output pairs switching. When an LVDS
or LVPECL output pair is disabled, the disable state is Qx/nQx = Hi-Z. It
should also be noted that the feedback output pins (FBOUT/nFBOUT) are
always switching and are not affected by the state of OE[2:0]. Refer to table
3B for truth table. LVCMOS/LVTTL Interface levels
IDT™ / ICS™ LVDS/LVPECL ZERO DELAY BUFFER/CLOCK GENERATOR 3
ICS8743008DKI REV. A AUGUST 25, 2008