ICS5342 Datasheet, PDF (9/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

AC Electrical Characteristics (note: J)
Parameter
Symbol
XIN input clock fall
time
t_XCLKF*
* Characterized values only
80 MHZ
Min Max
15
110MHz
Min Max
15
ICS5342
GENDAC
135Mhz
Min Max
15
Units
ns
Test
Conditions
TTL levels
Notes:
A. Full scale error is derived from design equation:
{[(F.S.I_OUT)R_L – 2.1(I_REF)R_L] / [2.1(I_REF)R_L]} 100%
V_{BLACK LEVEL}= 0 V
F.S.I_OUT = Actual full scale measured output
B. R= 37.5 Ω, I_REF = – 8.88 mA
C. Z_I = 37.5 Ω + 30 pF, I_REF = – 8.88 mA
D. This parameter is the allowed Pixel Clock frequency
variation. It does not permit the Pixel Clock period to
vary outside the minimum values for Pixel Clock
(t_CHCH) period.
E. The color palette’s pixel address is required to be a valid
logic level with the appropriate setup and hold times at
each rising edge of PCLK (this requirement includes the
blanking period).
F. The output delay is measured from the 50% point of the
rising edge of CLOCK to the valid analog output. A
valid analog output is defined when the analog signal is
halfway between its successive values.
G. This applies to different analog outputs on the same
device.
H. Measured at ± 200 mV from steady state output voltage.
I. This parameter allows synchronization between opera-
tions on the microprocessor interface and the pixel
stream being processed by the color palette.
J. The following specifications apply for V_DD = +5V±
0.5V, GND=0. Operating Temperature = 0˚C to 70˚C.
K. Except for SENSE pin.
AC Test Conditions
Input pulse levels...................................................V_DD to 3V
Input rise and fall times (10% to 90%) ............................ 3 ns
Digital input timing reference level ............................... 1.5 V
Digital output timing reference level .............0.8 V and 2.4 V
Capacitance
C₁ Digital input ............................................................... 7 pF
C₀ Digital output ............................................................. 7 pF
C_0A Analog output ........................................................ 10 pF
CLK
25 pF
1.4V
200 Ω
5342_03
Clock Load
General Operation
The ICS5342 GENDAC is intended for use as the analog out-
put stage of raster scan video systems. It contains a high-
speed Random Access Memory of 256 x 18-bit words, three
6/8-bit high-speed DACs, a microprocessor/graphic control-
ler interface, a pixel word mask, on-chip comparators, and
two user programmable frequency generators.
An externally generated BLANK* signal can be applied to
pin 7 of the ICS5342. This signal acts on all three of the ana-
log outputs. The BLANK* signal is delayed internally so that
it appears with the correct relationship to the pixel bit stream
at the analog outputs.
A pixel word mask is included to allow the incoming pixel
address to be masked. This permits rapid changes to the effec-
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