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ICS5342 Datasheet, PDF (8/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC
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ICS5342
GENDAC
AC Electrical Characteristics (note: J)
Parameter
Symbol
Differential output
delay
WR* pulse width low
RD* pulse width low
Register select setup
time
Register select setup
time
Register select hold
time
Register select hold
time
WR* data setup time
WR* data hold time
Output turn-on delay
RD* enable access time
Output hold time
Output turn-off delay
Successive write inter-
val
WR* followed by read
interval
Successive read interval
∆tCHAV
tWLWH
tRLRH
tSVWL
tSVRL
tWLSX
tRLSX
tDVWH
tWHDX
tRLQX
tRLQV
tRHQX
tRHQZ
tWHWL1
tWHRL1
tRHRL1
RD* followed by write
interval
WR* after color write
tRHWL1
tWHWL2
RD* after color write tWHRL2
RD* after color read
tRHRL2
WR* after color read
tRHWL2
RD* after read address
write
SENSE* output delay
XIN input clock rise
time
tWHRL3
tSOD
tXCLKR*
80 MHZ
Min Max
2
110MHz
Min Max
2
135Mhz
Min Max
2
Units
ns
Test
Conditions
note G
50
50
50
ns
50
50
50
ns
10
10
10
ns
write cycle
10
10
10
ns
read cycle
10
10
10
ns
write cycle
10
10
10
ns
read cycle
10
10
5
40
3
20
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
8
(tCHCH)
8
(tCHCH)
8
(tCHCH)
1
15
10
10
5
40
3
20
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
8
(tCHCH)
8
(tCHCH)
8
(tCHCH)
1
15
10
10
5
40
3
20
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
4
(tCHCH)
8
(tCHCH)
8
(tCHCH)
8
(tCHCH)
1
15
ns
ns
ns
ns
ns
ns
cycle
note H
note I
cycle note I
cycle note I
cycle note I
cycle note I
cycle note I
cycle note I
cycle note I
cycle note I
µs
ns
TTL levels
8
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