ICS5342 Datasheet, PDF (1/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
16-Bit Integrated Clock-LUT-DAC
General Description
Features
The ICS5342 GENDAC is a combination of dual programma- _{• Triple video DAC, dual clock generator, and 16 bit pixel}
ble clock generators, a 256 x 18-bit RAM, and a triple 8-bit
port
video DAC. The GENDAC supports 8-bit pseudo color appli- _{• Dynamic mode switch allows switching of color depth}
cations, as well as 15-bit, 16-bit, and 24-bit True Color bypass
on a pixel by pixel basis
for high speed, direct access to the DACs.
• 24 (packed and sparse), 16, 15, or 8-bit pseudo color
The RAM makes it possible to display 256 colors selected
from a possible 262,144 colors. The dual clock generators use
Phase Locked Loop (PLL) technology to provide program-
mable frequencies for use in the graphics subsystem. The vid-
pixel mode supports True Color, Hi-Color, and VGA
modes
• High speed 256 x 6 x 3 color palette (135 MHz) with
bypass mode and 8-bit DACs
eo clock contains 8 frequencies, all of which are • Eight programmable video (pixel) clock frequencies
programmable by the user. The memory clock has two pro-
(CLK0)
grammable frequency locations.
• DAC power down in blanking mode
The three 8-bit DACs on the ICS5342 are capable of driving
singly or doubly-terminated 75Ω loads to nominal 0 - 0.7
volts at pixel rates up to 135 MHz. Differential and integral
linearity errors are less than 1 LSB over full temperature and
VDD ranges. Monotonicity is guaranteed by design. On-chip
pixel mask register allows displayed colors to be changed in
a single write cycle rather than by modifying the color palette.
• Anti-sparkle circuitry
• On-chip loop filters reduce external components
• Standard CPU interface
• Single external crystal (typically 14.318 MHz)
• Monitor sense
• Internal voltage reference
ICS is the world leader in all aspects of frequency (clock) gen-
eration for graphics, using patented techniques to produce
low jitter video timing.
• 135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions
• Very low clock jitter
• Two latched frequency select pins or three non-latched
frequency select pins (programmable)
• Hardware video checksum for manufacturing tests
Block Schematic
PCLK
P0-P15
D0-D7
WR*
RD*
RS0-RS2
STROBE
CS0-CS2
XIN
XOUT
BUFF.
LATCH
MICRO-
8
PROCESSOR
INTERFACE
16
24
BYPS
PIXEL
ADR
AND
MASK
COLOR
PALETTE
256 x 18 ¹⁸
BIT
MUX
NORM
CTL
2X
BLANK*
16
8 PLL
PARAMETER &
CLK0 PLL
XTAL
OSC
1 PLL
PARAMETER &
CLK1 PLL
COMPARE SENSE*
LATCH
TRIPLE
24 ^6/8-BIT
DAC
RED
GREEN
BLUE
RSET
VREF
TIMING
GEN.
MUX.
PCLK
MODE
CLK0
CLK1
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