ICS5342 Datasheet, PDF (7/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
DAC Characteristics
Parameter
Symbol
Min
Maximum output voltage
Maximum output current
Full scale error
DAC to DAC correlation
Integral Linearity, 6-bit
Integral Linearity, 8-bit
Full scale settling time*, 6-bit
Full scale settling time*, 8-bit
Rise time (10% to 90%)*
Glitch energy*
V_o (max)
I_o (max)
PLL AC Characteristics
Parameter
Clock 0 operating range
Clock 1 operating range
Output clocks rise time*
Output clocks fall time*
Duty Cycle*
Jitter, one sigma*
Jitter, absolute*
Input reference frequency*
* Characterized values only
Symbol
f0
f₁
t_r
t_r
d_t
j_1s
j_abs
f_ref
Min
25
25
40/60
-300 ps
5
Max
1.5
21
±5
±2
± 0.5
±1
28
20
6
200
Max
135
135
3
3
60/40
130 ps
300 ps
25
Units
V
mA
%
%
LSB
LSB
ns
ns
ns
pV.s
Test Conditions
I_o ≤ 10 mA
V_o ≤ 1V
note A, B
note B
note B
note B
note C
note C
note C
note C
Units
MHz
MHz
ns
ns
%
ps
ps
MHz
Test Conditions
25 pF load, TTL levels
25 pF load, TTL levels
Typically 14.318 MHz
AC Electrical Characteristics (note: J)
Parameter
PCLK period
PCLK jitter
PCLK width low
PCLK width high
Pixel word setup time
Pixel word hold time
BLANK* setup time
BLANK* hold time
PCLK to valid DAC
output
Symbol
t_CHCH
∆t_CHCH*
t_CLCH
t_CHCL
t_PVCH
t_CHPX
t_BVCH
t_CHBX
t_CHAV*
80 MHZ
Min
12.5
5
5
3
3
3
3
Max
± 2.5
20
110MHz
Min
9.09
3.6
3.6
3
2
3
2
Max
+2.5
20
135Mhz
Min Max
7.4
3
3
2
1
2
1
20
Units
ns
%
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
note D
note E
note E
note E
note E
note F
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