ICS5342 Datasheet, PDF (17/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
Frequency Generators
The ICS5342 clock synthesizer can be reprogrammed through
the microprocessor interface for any set of frequencies. This
is done by writing appropriate values to the PLL Parameter
Register Bank (See following table: “PLL Parameter Regis-
ters”).
PLL Address Registers
The address of the parameter register is written to the PLL ad-
dress registers before accessing the parameter register. This
register is accessed by register select pins RS2-RS0 = 100 or
111.
PLL Address Register
76543210
PLL Register Adr.
76543210
PLL Parameters Registers
There are sixteen registers in the PLL parameter register (ta-
ble 5). Registers 00 to 07 are for the CLK0 selectable frequen-
cy list, Register 0A and 0B for CLK1 programmable
frequency and register 0E is the PLL control register.
PLL Parameter Registers
Index
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/-
R/W
R/W
R/W
R/-
R/-
R/W
R/-
Register
CLK0 f0 PLL Parameters
CLK0 f1 PLL Parameters
CLK0 f2 PLL Parameters
CLK0 f3 PLL Parameters
CLK0 f4 PLL Parameters
CLK0 f5 PLL Parameters
CLK0 f6 PLL Parameters
CLK0 f7 PLL Parameters
(Reserved) = 0
CLK1 fA PLL
CLK1 fB PLL
(Reserved) = 0
(Reserved) = 0
(Reserved) = 0
PLL Control Register
(Reserved) = 0
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes)
(2 bytes
(2 bytes)
(2 bytes)
(2 bytes
(2 bytes)
(2 bytes)
(1-byte)
(2 bytes)
PLL Control Register
Bits in this register determine internal or external CLK0 se-
lect.
PLL Control Register
76543210
(RV)= (RV)= ENBL CLK1 (RV)= Internal Select
00
INCS SEL 0 X X X
Bit 7,6, 3 Reserved, set to ‘0’ for future compatibility.
Bit 5
Enable Internal Clock Select (INCS) for CLK0.
When this bit is set to 1, the CLK0 output fre-
quency is selected by bits 2-0 in this register.
External pins CS0-CS2 are ignored.
Bit 4
Clk1 Select when this bit is set to 0, fA is
selected. When it is set to 1, fB is selected. The
default is 0 for fA selected at power up.
Bit 2 - 0
Internal Clock Select for CLK0 (INCS). These
three bits select the CLK0 output frequency if bit
5 of this register is on. They are interpreted as an
octal number, n, that selects fn. Default selects f0.
PLL Data Registers
The CLK0 and CLK1 output frequency is determined by the
parameter values in this register. These are two-byte registers;
the first byte is the M-byte and the second the N-byte.
M-Byte PLL Parameter Input
The M-byte has a 7-bit value (1-127) which is the feedback
divider of the PLL.
M-Byte
7
6543210
Reserved
M-Divider Value
=0
XXXXXXX
N-Byte PLL Parameter Input
The N-byte contains two parameter values. N1 sets a 5-bit val-
ue (1-31) for the input pre scalar and N2 is a 2-bit code for se-
lecting 1, 2, 4, or 8 post divide clock output.
N-Byte PLL Parameter Input
7
6543210
Reserved N2 - Code
N1-Divider Value
=0
XXXXXXX
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