ICS5342 Datasheet, PDF (3/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
Pin Description (68-pin PLCC)
Symbol
CLK1
CLK0
CS0
CS1
VREF
RSET
SENSE*
Pin #
11
8
2
3
46
42
68
Type
Output
Output
Input
Input
I/O
Input
Output
BLUE
GREEN
RED
P15- P0
PCLK
40
38
37
13,12,4,1
,
67-64,
58-51
Output
Output
Output
Input
59
Input
STROBE* 6
BLANK* 7
Input
Input
CVDD
CVDD
AVDD
DVDD
XVDD
CVDD
CGND
CGND
XGND
AGND
DGND
CGND
N/C
9
-
27
-
41
-
43
-
50
-
61
-
10
-
26
-
47
-
36
-
44
-
60
-
28-35, -
39,45,
62
Description
Memory clock output – used to time video memory
Video clock output – provides a CMOS level pixel or dot clock frequency to
graphics controller – output frequency is determined by values of PLL registers
Clock select 0 – The status of CS0-1 determines which frequency is selected on
the CLK0 (video) output.
Clock select 1– status of CS0-1 determines which frequency is selected on CLK0
(video) output
Internal reference voltage – normally connects to a 0.1µf capacitor to ground – to
use external Vref, connect 1.235V reference to this pin
Resistor set – pin used to set current level in analog outputs – usually connected
through 1/4W, 1% resistor to ground
Monitor sense – Pin is active low when any of red, green, or blue outputs >385mV.
Sense output is high when all analog outputs are < 275 mV. Chip has on-board
comparators and internal 1.235 V voltage reference. This signal is used to detect
monitor type.
Color signals from DAC analog outputs – Each DAC comprises several current
sources of which outputs are added together according to the applied binary value.
The outputs are typically used to drive a CRT monitor.
Pixel address lines – Byte-wide information is latched by the rising edge of PCLK
when using the color palette, and is masked by the Pixel Mask register. Values are
used to specify the RAM word address in default mode (accessing RAM). In Hi-
Color XGA, and True Color modes, they represent color data for the DACs.
Ground inputs if they are not used.
Pixel Clock – rising edge of PCLK controls latching of the Pixel Address and
BLANK* inputs – clock also controls progress of these values through the three-
stage pipeline of the Color Palette RAM, DAC, and outputs
latches input clock select signals CS0-CS1
Composite BLANK* Signal, active low. When BLANK* is asserted, outputs of
DACs are zero which blacks screen. DACs are automatically powered down to
save current during blanking. Color palette may still be updated through D0-D7
during blanking.
CLK1 Power Supply – connect to DVDD
CLK0 power supply – connect to AVDD
DAC power supply – Connect to AVDD
Digital power supply
Crystal oscillator power supply– connect to AVDD
CLK power supply – connect to DVDD
VSS for CLK1 – connect to ground.
VSS for CLK0 – connect to ground
VSS for crystal oscillator
DAC ground – connect to ground
Digital ground – connect to ground
VSS for CLK – connect to ground
Not connected – leave floating or tie to ground
3