ICS5342 Datasheet, PDF (2/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
Pin Configuration
Pin Configuration
CGND 10
CLK1 11
P14 12
P15 13
D0 14
D1 15
D2 16
D3 17
D4 18
D5 19
D6 20
D7 21
WR* 22
RS0 23
RS1 24
MSW 25
CGND 26
GENDAC II
ICS5342
60 CGND
59 ^PCLK
58 ^P7
57 ^P6
56 P5
55 P4
54 P3
53 P2
52 P1
51 P0
50 XVDD
49 XOUT
48 XIN
47 XGND
46 VREF
45 N/C
44 DGND
ICS5342 (68-pin PLCC)
5342_02
Pin Description (68-pin PLCC)
Symbol
D7 - D0
Pin #
21-14
Type
I/O
RD
WR
RS2-RS0
XIN
XOUT
MSW
5
Input
22
Input
63,24,23 Input
48
Input
49
Output
25
Input
Description
Systems data bus bidirectional data I/O lines – used by host microprocessor for
internal register read and write operations (using active low RD and WR respec-
tively) for six internal registers: Pixel Address, Color Value, Pixel Mask, PLL
Address, PLL Parameter, and Command
During the write cycle, the rising edge of WR latches the data into the selected
register (set by the status of the three RS pins).
The rising edge of RD determines the end of the read cycle.
The RD set logical high indicates that data I/O lines no longer contain infor-
mation from the selected register and will be tri-stated.
RAM/PLL read enable bus control signal – in active low state, any information
present on the internal data bus is available on the Data I/O lines, D0-D7
Active low RAM/PLL write enable bus control signal – controls write timing on
microprocessor interface inputs, D0-D7
Register address select 0 inputs – control selection of one of six internal registers –
inputs are sampled on falling edge of active enable signal (RD or WR)
Crystal input – connect to 14.318 MHz crystal
Crystal output – connect to 14.318 MHz crystal
Mode switch – digital control for selecting primary and secondary pixel color
modes – low selects primary mode – connect to ground if not used
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