ICS5342 Datasheet, PDF (15/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
Color Modes
The nine selectable color modes are described here. Four are
eight-bit and five are 16-bit wide pixel input. Color Modes 0-3
are 8-bit interfaces with bits P0-P7; P8-P15 are “don’t care”
bits.
16-Bit Color - Mode 2
SECOND BYTE FIRST BYTE
PPPPPPPPPPPPPPPP
7654321076543210
7654376543276543
RED
GREEN BLUE
Mode 0: 8-bit Pseudo Color (one clock per pixel). This mode
is the 8-bit per pixel Pseudo Color mode. In this mode, inputs
P0-P7 are the pixel address for the color palette RAM and are
latched on the rising edge of every PCLK. This is the default
mode on power up and it is selected by setting bits CR7-CR4
to 0000.
8-bit Pseudo Color
- Mode 0
PIXEL BYTE
PPPPPPPP
76543210
76543210
LUT ADDRESS
Mode 1: (15-bit per color bypass Hi-Color mode). This mode
is the 15-bit per pixel bypass mode. In this mode, inputs P0-P7
are the color DATA and are input directly to the DAC, by-
passing the color palette. The two bytes of data are latched in
two successive PCLK rising edges. ICS5342 supports only
the two clock mode and does not support the mode where the
data are latched on the rising and the falling edges. For com-
patibility, the 15/16 one clock modes are selected as two clock
modes in this chip. The low-byte, high byte synchronization
is internally done by the rising edge of BLANK*. Each color
is 5-bit wide and is packed into two bytes as shown below.
This mode can be selected by setting bits CR7-CR4 to 0010,
1000 or 1010.
15-Bit Color - Mode 1
SECOND BYTE FIRST BYTE
PPPPPPPPPPPPPPPP
7654321076543210
X7 6 5 4 3 7 6 5 4 3 7 6 5 4 3
X RED
GREEN BLUE
3LSB = set to zero
Mode 2: (16-bit per pixel bypass XGA mode). This mode is
the 16-bit per pixel bypass mode and the P0-P7 inputs to go to
the DAC directly, bypassing the color palette. The 2 bytes
data is latched on two successive rising edges and the low-
byte, high-byte synchronization is internally done by the ris-
ing edge of BLANK*. In this mode, blue and red colors are 5
bits wide and green is 6 bits wide. The 2 bytes of data are
packed as shown below. This mode can be selected by setting
bits CR7-CR4 to 0110 or 1100.
2LSB = set to zero (green)
3LSB = set to zero (blue, red)
Mode 3: (24-bit per pixel True Color Mode). This mode is the
24-bit per pixel bypass mode. The three bytes of data are
latched on three successive PCLK edges and the first byte is
synchronized by the rising edge of BLANK*. In this mode,
each of the colors are 8-bit wide and the DAC is an 8-bit wide
DAC. The first byte is blue followed by green and red. This
mode can be selected by setting bits CR7-CR4 to 0100 or
1110. The DAC outputs changes every three cycles and the
pipeline delay from the first byte to output is five cycles.
24-bit Color - Mode 3
THIRD BYTE SECOND BYTE FIRST BYTE
PPPPPPPPPPPPPPPPPPPPPPPP
765432107654321076543210
765432107654321076543210
RED
GREEN
BLUE
16 bit Color Modes
Modes 4 - 8 use the 16-bit pixel interface.
Mode 4: (8-bit Pseudo Color two pixels per clock) In this
mode, inputs P0-P15 are latched on the rising edge of every
PCLK. P0-7 and P8-P15 are used for successive addresses for
the palette RAM using an internal clock (ICLK) that runs at
twice the PCLK frequency. The DAC outputs change twice
for every PCLK and the pipeline delay from the first word to
output is one and one half cycles. This mode can be selected
by setting bits CR7-CR4 to 0001.
Multiplexed 8-bit Pseudo Color Word
- Mode 4
PIXEL WORD
PPPPPPPPPPPPPPPP
1111119876543210
543210
7654321076543210
2nd PIXEL
1st PIXEL
ADDRESS
ADDRESS
Mode 5: (16-bit pixel interface, 15-bit per color bypass Hi-
Color Mode) In this mode inputs P0-P15 are the color data
and are input directly to the DAC, bypassing the color palette.
The data is latched by the rising edge of PCLK and is pipe-
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