ICS5342 Datasheet, PDF (33/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
Note the power plane is not separated into analog and digital
supply regions. The power and ground planes are continuous,
not split. Power is supplied to the analog power pins through
the ferrite bead, and bypassed at the power entry point by C3,
a 10 µF tantalum capacitor. Analog power connections should
be routed as shown in the diagram. They may be routed on the
back side so the analog signals are routed without vias. Power
pins 9 and 43 should be connected to digital power. Power
pins 27, 41 and 50 are connected to analog power (VAA). Ce-
ramic decoupling capacitors (indicated by C1 and C2) should
be placed as close to the GENDAC as possible. The power
traces should be routed through the capacitor pads and the
ground vias should not be shared. The rule is: one pad, one
via. The GENDAC analog ground pins should have multiple
vias to the ground plane, if possible.
To supply the transient currents required, the impedance in
the decoupling path should be kept to a minimum. It is just as
important that the connection between the capacitor ground
pad and the ground plane be short and direct. It is recommend-
ed that the decoupling capacitance between V_DD and GND
should be a 0.047 µF to 0.1 µF high frequency capacitor. Chip
capacitors have the lowest lead inductance and are highly rec-
ommended. 0.047 µF chip capacitors are more effective at fre-
quencies above 80 MHz than other values in the range of
0.022 µF to 0.1 µF. All supply pins must have a ceramic ca-
pacitor connected. A tantalum capacitor with a value between
10 µF and 22 µF is recommended to decouple low frequen-
cies. To further reduce power-supply noise, a ferrite bead may
be added in series with the positive supply to form a low pass
filter, as shown in the layout example. Power and ground trac-
es to the GENDAC should be 50 mils wide whenever possi-
ble.
Analog Signals
All analog and digital I/O lines are not shown. Analog signals
(DAC outputs, V_REF, R_SET) should only be routed on the top
side of the board. DAC output termination resistors should be
located as close as possible to the GENDAC for best signal
quality. Doing this will also reduce RFI.
Digital Input Information
To minimize differential ground noise between components
on the board, the impedance in the ground supply between the
GENDAC and the digital devices driving it should be mini-
mized. This or a high impedance ground trace on the control-
ler may cause false signals to the GENDAC. This can appear
as glitches on edge sensitive inputs such as RD*, WR*, and
STRB. Splitting the ground plane exacerbates this problem.
The combination of series impedance in the ground supply to
the GENDAC and transients in the current drawn by the de-
vice, will appear as voltage differences across the GND pins
on the GENDAC. The effect this will have is to compromise
the low time and duty cycle of the output clocks.
The PCB traces between the outputs of the TTL devices driv-
ing the GENDAC and the input to the GENDAC behave like
low impedance transmission lines. The trace is driven from a
low impedance source and terminated with a high impedance.
In accordance with transmission line principles, signal transi-
tions will be reflected from the high impedance input to the
device. Similarly, signal transitions will be inverted and re-
flected from the low impedance TTL output. Termination is
necessary to reduce or eliminate ringing; particularly the un-
dershoot caused by reflections. Termination may either be se-
ries or parallel. Series and parallel termination is the
recommended technique to use. This is accomplished by plac-
ing a resistor in series with the signal at the output of the clock
driver. The resistor matches the output buffer impedance to
that of the transmission line. At the far end of the line another
resistor is added to terminate the transmission line to VCC.
To minimize reflections, some experimentation is necessary
to find the proper value to use for the series termination. Gen-
erally, a series resistor with a value around 75Ω, and a parallel
resistor of 330Ω will be satisfactory. Since each design will
result in a different trace impedance, a resistor of a predeter-
mined value may not properly match the signal path imped-
ance. The proper value of resistance should be found
empirically.
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