ICS5342 Datasheet, PDF (10/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
tive contents of the color palette RAM to facilitate such oper-
ations as animation and flashing objects. Operations on the
contents of the mask register can also be totally asynchronous
to the pixel stream.
The ICS5342 also includes dual PLL frequency generators
providing a video clock (CLK0) and a memory clock (CLK1),
both generated from a single 14.318 MHz crystal. There are
eight selectable CLK0 frequencies. All eight are programma-
ble. There are two selectable and programmable CLK1 fre-
quencies (fA, fB). Default values (Shown in tables: “Video
Clock Default Frequency Registers,” and “Memory Clock
Default Frequency Registers”) are loaded into the appropriate
registers on power up.
Video Path
The GENDAC supports nine different video modes and is de-
termined by bits 4-7 of the command register. The default
mode is the 8-bit Pseudo Color mode. The other modes are the
bypass 15-bit, 16-bit and 24 bit True Color modes in 8-bit and
16-bit interface, and the 16-bit Pseudo Color (2:1) mode with
2X Clock. The 24-bit True Color has sparse and packed
modes.
Pseudo Color
8-bit Interface
In this mode, Pixel Address, P7-P0 and BLANK* inputs are
sampled on the rising edge of the clock (PCLK) and any
change appears at the analog outputs after three succeeding
rising edges of the PCLK. The DAC output depends on the
data in the color palette RAM.
16-bit Interface
In this mode, Pixel Address, P15-P0 and BLANK* inputs are
sampled on the rising edge of the clock (PCLK) and any
change appears at the analog outputs after three succeeding
rising edges of the 2 x ICLK. ICLK frequency is twice the
PCLK input frequency. The DAC output depends on the data
in the color palette RAM.
Bypass Mode
The GENDAC supports seven different bypass modes: three
for byte transfers and four for word transfers. In these modes,
the address pins P0-P15 represent Color Data that is applied
directly to the DAC. The internal look-up table RAM is ig-
nored. During byte transfers, the P8-P15 inputs are”don't
care.” Data is always latched on the rising edge of PCLK.
Byte or word framing is internally synchronized with the ris-
ing edge of BLANK*.
DAC Outputs
The outputs of the DACs are designed to be capable of pro-
ducing 0.7 V peak white amplitude with an I_REF of 8.88 mA
when driving a doubly-terminated 75 Ω load. This corre-
sponds to an effective DAC output load (R_EFFECTIVE) of 37.5
Ω. The formula for calculating I_REF with various peak white
voltage/output loading combinations is given below:
I_REF = -2--.--1--^V--_×--^P---^E_R---^A-_E--^K--_F--^W-_F---_EH---_C-^I--^T-_T--^E-_I--_V---_E-
Note that for all values of I_REF and output loading:
V_BLACKLEVEL = 0
The reference current I_REF is determined by the reference
voltage V_REF and the value of the resistor connected to R_SET
pin. V_REF can be the internal band gap reference voltage or
can be overridden by an external voltage. In both cases:
I_REF = V_REF ⁄ R_SET
V_REF
(INT)
33
V_REF
(EXT)
I_REF
DAC ³⁶
38
39
I_REF
34
R_SET
R_EFF
DAC Setup
5342_04
The BLANK* input to the GENDAC acts on all three of the
DAC outputs. When the BLANK* input is low, the DACs are
powered down.
The connection between the DAC outputs of the ICS5342 and
the RGB inputs of the monitor should be regarded as a trans-
mission line. Impedance changes along the transmission line
will result in the reflection of part of the video signal back
along the line. These reflections may result in a degradation
of the picture displayed by the monitor.
RF techniques should be observed to ensure good fidelity.
The PCB trace connecting the GENDAC to the off-board con-
nector should be sized to form a transmission line of the cor-
rect impedance. Correctly matched RF connectors should be
used for connection from the PCB to the monitor coaxial cable
and from that cable to the monitor.
There are two recommended methods of DAC termination:
double termination and buffered signal. Each is described be-
low with its relative merits.
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