ICS5342 Datasheet, PDF (18/36 Pages) Integrated Circuit Systems – 16-Bit Integrated Clock-LUT-DAC

ICS5342
GENDAC
N2 Post Divide Code
If mode 4 is set in the command register, CR7-CR4 bits equal
0001, and the N2 code must be 10.
N2 Post Divide Code
N2 Code
00
01
10
11
Divider
1
2
4
8
The block diagram of the PLL clock synthesizer is shown in
figure 3.
Based on the M and N values, the output frequency of the
clocks is given by the following equation:
F_OUT
=
-⁽--^M-------+-----2---⁾--^F----^R----^E---^F-
2^N2(N1 + 2)
M and N values should be programmed such that the frequen-
cy of the VC0 is within the optimum range for duty cycle, jit-
ter and glitch free transition. Optimum duty cycle is achieved
by programming N2 for values greater than unity. See the next
section for a programming example.
Programming Example
Suppose an output frequency of 25.175 MHz is desired. The
reference crystal is 14.318 MHz. The VCO should be targeted
to run in the 60 to 270 MHz range, so choosing a post divide
of 4 gives a VCO frequency of:
4 × 25.175 = 101.021 MHz
From the table in the previous section, we find N2 = 2 Substi-
tuting F_REF = 14.318 and 2^N2 = 4 into the clock frequency
equation in the previous section:
Additional Information on Programming
the Frequency Generator section of the
GENDAC
When programming the GENDAC PLL parameter registers,
there are many possible combinations of parameters which
will give the correct output frequency. Some combinations are
better than others, however. Here is a method to determine
how the registers need to be set:
The key guidelines come from the operation of the phase
locked loop, which has the following restrictions:
1. 2 MHz < f _REF < 25 MHz This refers to the input refer-
ence frequency. Most users simply connect a 14.318
MHz crystal to the crystal inputs, so this is not a prob-
lem.
2.
600KHz ≤
---^f---^R---^E----^F---
N1 + 2
≤ 8MHz
This
is
the
frequency
input
to
the phase detector.
3.
60
MHz
≤
--^M------+-----2---
N1 + 2
〈
f
RE
F^〉
≤
270
MHz
This is the VCO
frequency. In general, the VCO should run as fast as pos-
sible, because it has lower jitter at higher frequencies.
Also, running the VCO at multiples of the desired fre-
quency allows the use of output divides, which tends to
improve the duty cycle.
4. f _CLK0 and f _CLK1 ≤ 35 MHz This is the output fre-
quency.
These rules lead to the following procedure for determining
the PLL parameters, assuming rules 1 and 4 are satisfied.
A. Determine the value of N2 (either 1, 2, 4 or 8) by select-
ing the highest value of N2, which satisfies the condition
N2* fCLK < 270 Mhz.
2---5---.--1---7---5-
14.318
〈
4〉
=
--^M------+-----2---
N1 + 2
By trial and error:
M + 2 = 127 M = 125
N1 + 2 = 18 N1 = 16
so the registers are:
M = 125d = 1 1 1 1 1 0 1 b
N = 0 & N2 code & N1 = 0 & 1 0 & 1 0 0 0 0
N=01010000b
B. Calculate:
--^M------+-----2--- = -2---^N----²---^f---^O----^U---^T--
N1 + 2
f _REF
C. Now (M+2) and (N1+2) must be found by trial and error.
With a 14.318 MHz reference frequency, there will gen-
erally be a small output frequency error due to the reso-
lution limit of (M+2) and (N1+2). For a given frequency
tolerance, several different (M+2) and (N1+2) combina-
tions can usually be found. Usually, a few minutes trying
18