IC-MV Datasheet, PDF (7/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
preliminary
Rev B1, Page 7/28
ELECTRICAL CHARACTERISTICS
Operating condition: VDD = 5 V ±10 %, Tj = -40...125 °C, 4 mm NdFeB magnet unless otherwise noted.
Item Symbol Parameter
No.
Conditions
Min.
General
001 V(VDD) Permissible Supply Voltage VDD
4.5
002 I(VDD)
Supply Current in VDD
Normal Mode
normal mode (LOPM = 0x0), without load
003 I(VDD)
Supply Current in VDD
Low Power Mode
low power mode (LOPM = 0x1), without load
004 I(VDD) Supply Current in VDD
NOSBY = 0x0, NERR = lo, ENPU = 0x0
005 Vc()hi
Clamp-Voltage hi at SLO, SDA, Vc()hi = V() − V(VPD), I() = 1 mA
0.4
SCL, ADR0, ADR1, SLI, SCLK
006 Vc()lo
Clamp-Voltage lo at SLO, NERR, I() = -1 mA
-1.5
SDA, SCL, ADR0, ADR1, SLI,
SCLK
Hall Sensor Array and Signal Conditioning
101 Hext
Permissible Magnetic Field
at chip surface
20
Strength
102 fmag
Operating Magnetic Field
Frequency
LOPM = 0x0
LOPM = 0x1
103 rpm
Rotating Speed of Magnet
LOPM = 0x0
LOPM = 0x1
104 dsens
Diameter of Hall Sensor Circle
105 xdis
Permissible Lateral Displacement 4 mm magnet
of Magnet Axis to Center of Hall
Sensors
106 xpac
Displacement Chip Center to
Package Center
package QFN16
-0.05
107 ϕpac
Angular Alignment of Chip vs. package QFN16
-0.6
Package
108 hpac
Distance Chip Surface to
Package Surface
package QFN16
Automatic Gain Control
201 tampl
Settling Time of Gain Control to 70 % of final amplitude
202 V()gain Gain Output Voltage
TEST = 0b001 measurable at NERR or
0.1
TEST = 0b011 measurable at SCLK
Sine-to-Digital Converter
801 RESsdc Converter Resolution
802 AAabs Absolute Angular Accuracy
(LOPM = 0x00) Vpp(VTS, VTC) = 4 V calibrated -2.8
803 AAabs Absolute Angular Accuracy
(LOPM = 0x01) Vpp(VTS, VTC) = 4 V calibrated -3.5
804 AArel
Relative Angle Error
(LOPM = 0x00) ideal input signals, quasi static -15
805 AArel
Relative Angle Error
(LOPM = 0x01) ideal input signals, quasi static -35
Power Down Reset
901 Vref(SLI) Reference Voltage
TEST = 0b011
45
902 VDDon Turn-on Threshold VDD
increasing voltage
3.3
(Power-Up-Enable)
903 VDDoff Turn-off Threshold VDD
decreasing voltage
2.8
(Power-Down-Reset)
904 VDDhys Turn-on Threshold Hysteresis
0.3
Serial Interface: SCLK, SLO, SLI
A01 Vs()hi
Saturation Voltage hi
Vs()hi = V(VPD) − V(), I() = -1.6 mA
A02 Vs()lo
Saturation Voltage lo
I() = 1.6 mA
A03 Isc()lo
Short-Circuit Current lo
V() = VDD
10
A04 Isc()hi
Short-Circuit Current hi
V() = 0 V
-90
A05 tr()
Rise Time at SLO
CL = 50 pF
A06 tf()
Fall Time at SLO
CL = 50 pF
Typ.
4
2
0.4
1.5
0.4
200
8
50
3.8
3.4
Unit
Max.
5.5
V
6
mA
4
mA
1.4 mA
1.5
V
-0.3
V
100 kA/m
400 Hz
50
Hz
24000 rpm
3000 rpm
mm
0.2 mm
0.05 mm
0.6 deg
mm
500
µs
4.0
V
bit
2.8 deg
3.5 deg
15
%
35
%
55 %VDD
4.4
V
4.1
V
V
0.4
V
0.4
V
90
mA
-10 mA
60
ns
60
ns