IC-MV Datasheet, PDF (21/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
ERROR HANDLING
preliminary
Rev B1, Page 21/28
CRC Error
If the EEPROM is not read out at all or not entirely or if
a CRC error is detected, the SSI interface provides a
steady high level at request.
EMODE
Code
0x00
0x01
0x03
0x05
0x07
Addr. 0x01; bit 5:3
Function
No error bit
1 serial error bit lo active
1 serial error bit hi active
n serial error bits lo active
n serial error bits hi active
Error Bit Options
If an amplitude error is recognized e.g. through the loss
of the magnet, this is displayed through a low level and
sent to the SSI protocol, if activated. The error bit is
configured via register bits EMODE(2:0), where n is the
number of the iC-MV slaves.
Table 20: Error Bit Options
The error bit is added to the position data. Thereby
iC-MV 1 in the SSI chain sends its error bit first. In case
additional iC-MVs exist, iC-MV 2 then sends its error bit
to the neighboring component.
SCAN TEST
In order to test digital components a scan path is inte-
grated. The scan test is activated when a voltage of
approx. 1 V above VDD is connected to the pin NERR.
SCAN TEST
Pin
Description
SCLK
Scan Clock
SLI
Scan Input
SLO
Scan Output
ADR1
Scan Enable
ADR0
Not Reset
Table 21: Pin Function in the Scan Test.