IC-MV Datasheet, PDF (22/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
APPLICATION EXAMPLES
preliminary
Rev B1, Page 22/28
iC-MHM with 4 iC-MVs
Supply
VDD
GND
BiSS-
Interface
MAO
NMAO
MA
NMA
SLI
NSLI
SLO
NSLO
Analog
Signals
SIN
NSIN
COS
NCOS
VDD
GND
MAO
NMAO
MA
NMA
SLI
NSLI
SLO
NSLO
BiSS
SIN
NSIN
COS
NCOS
SIN
COS
REVERSE POLARITY
PROTECTION
B
PSIN
B
PCOS
B
B
NCOS
NSIN
HALL SENSOR
12 BIT
SIN/DIG
0x00
0x0F
0x10
0x1F
0x77
0x7F
RAM
VDDS
GNDS
VDDS
S
SCL
I2C
SDA
MDI
MCL
MTI
iC-MHM
NERR
Error Monitor
VDDS
ERROR
VDDS
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 4
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
S
EEPROM
SDA
SCL
VDDS VDDS
VDDS
VDDS
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 3
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
S
S _VDDS
VDDS
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 2
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
GND
EEPROM INTERFACE
SCL SDA ADR0 ADR1
S
VDDS ^S
VDDS
NERR
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 1
SLO
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
S
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
S
S
S
Figure 18: iC-MHM with 4 iC-MVs
Note: Circuit examples are provided for illustration of principle. Additional components required for a successful
application may be omitted for clarity.