IC-MV Datasheet, PDF (19/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
ABZ INTERFACE
preliminary
Rev B1, Page 19/28
In MODE = 0x07 the ABZ interface is activated. An in-
cremental output occurs at SLI, SCLK and SLO. In ABZ
mode register bit SYNC extends the zero pulse about
90 °. The resolution can be adjusted via DL(2:0) like in
normal operation. The converter hysteresis is 1.4 ° and
the minimum threshold distance is two oscillator clocks.
SLI:
A
SCLK:
B
SLO:
Z
Figure 15: ABZ Signals
ADJUSTMENT
For the adjustment test mode is activated via MODE =
0x01. The automatic gain control’s signal gain is out-
put at pin NERR. In this test mode ENPU = 0x0 and
NOSBY = 0x1 must be set. The signal level on the
signal gain can be used as a measurement for the axial
adjustment between iC-MV and the magnet.
Justage: Radial
The radial adjustment is determined by the mechanical
arrangement of the system components (package, gear,
axis offset and PCB).
Adjustment: Axial
The GAIN signal should be set between approx. 200 mV
and 400 mV via axial adjustment. This corresponds to
a distance of about 1 mm.
Figure 16: Axial Adjustment
Figure 17: Radial Adjustment