IC-MV Datasheet, PDF (26/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
preliminary
MV1A with 4 iC-MVs
VDDS
VB_EXT_OUT
GND
MV1A
MO+
MO-
MA+
MA-
SL+
SL-
RESET
SEL_INTERFACE
5V-24V/300mA
VB_EXT_IN
GND
VDD
SLI
NSLI
MA
NMA
SL
NSL
GND
MB3U BiSS-
Interface
Rev B1, Page 26/28
EN_MTI
MTC
MTD
SCL
SDA
GND
EEPROM
VDD_I2C
IO3
IO1
IO2
SCLK
MOSI
GND
MB3U I2C-
Interface
VDDS
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 4
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
VDDS VDDS
VDDS
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 3
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
VDDS
VDDS
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 2
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
GND
EEPROM INTERFACE
SCL SDA ADR0 ADR1
VDDS
VDDS
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 1
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
Figure 22: MV1A with 4 iC-MVs
DESIGN REVIEW: Notes On Chip Functions
iC-MV Y1
No.
1
2
Function, Parameter/Code
GAIN
ENPU
Description and Application Hints
GAIN signal doubled in adjustment mode.
Current consumption reduced in standby mode with ENPU = 0x0.
Table 22: Notes on chip functions regarding iC-MV chip release Y1
iC-MV X2
No.
1
Function, Parameter/Code
Description and Application Hints
No further notes at time of printing.
Table 23: Notes on chip functions regarding iC-MV chip release X2