IC-MV Datasheet, PDF (10/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
CONFIGURATION
preliminary
Rev B1, Page 10/28
OFFSET:
DIR:
RNF:
EMODE:
DL:
ERRSY:
Position Offset (P. 14)
Code Direction (P. 14)
Edge of Data Output (P. 14)
Error Bit Options (P. 15)
Data Length (P. 15)
Synchronization Monitoring (P. 15)
NOSBY:
LOPM:
ENPU:
SYNC:
MODE:
Standby Enable (P. 15)
Low Power Mode (P. 15)
Pull-up Enable (P. 15)
Position Data Synchronization (P. 16)
Operating Mode (P. 17)
OVERVIEW
Addr
Bit 7
iC-MV 1: ADDR = 0b00
0x00
0x01
DIR
0x02
ERRSY
0x03
iC-MV 2: ADDR = 0b01
0x04
0x05
DIR
0x06
ERRSY
0x07
iC-MV 3: ADDR = 0b10
0x08
0x09
DIR
0x0A
ERRSY
0x0B
iC-MV 4: ADDR = 0b11
0x0C
0x0D
DIR
0x0E
ERRSY
0x0F
Bit 6
RNF
NOSBY
RNF
NOSBY
RNF
NOSBY
RNF
NOSBY
Bit 5
Bit 4
Bit 3
Bit 2
LOPM
OFFSET(7:0)
EMODE(2:0)
ENPU
SYNC
-
LOPM
OFFSET(7:0)
EMODE(2:0)
ENPU
SYNC
-
LOPM
OFFSET(7:0)
EMODE(2:0)
ENPU
SYNC
-
LOPM
OFFSET(7:0)
EMODE(2:0)
ENPU
SYNC
CRC(7:0) over Addr = 0x00 bis 0x0E
Bit 1
Bit 0
DL(2:0)
MODE(2:0)
DL(2:0)
MODE(2:0)
DL(2:0)
MODE(2:0)
DL(2:0)
MODE(2:0)
Table 5: Register layout
NERR
SLO
ADR=0b11
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 4
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
Hi Hi
NERR
SLO
ADR=0b10
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 3
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
Lo Hi
NERR
SLO
ADR=0b01
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 2
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
GND
EEPROM INTERFACE
SCL SDA ADR0 ADR1
Hi Lo
NERR
SLO
ADR=0b00
VDD
8 BIT
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 1
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
Lo Lo
EEPROM VDD
24CXX
SCL
SDA
GND
NERR
SCLK
SLO
Figure 2: I²C Device Addressing