IC-MV Datasheet, PDF (18/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
EEPROM INTERFACE AND DEVICE ADDRESSING
preliminary
Rev B1, Page 18/28
An external EEPROM is required for the configuration
of iC-MV. In the typical multiturn application, up to four
iC-MVs share one EEPROM. iC-MV 1 is assigned with
a low level at pins ADR1 and ADR0. Thus, 0b00 is the
address of the first iC-MV in the SSI chain. iC-MV 2 is
assigned with a low level at ADR1 and a high level at
ADR0 and hence the address 0b01 (see Figure 2). The
addresses for following iC-MVs can be generated from
Table 18 according to this principle.
At the beginning of every communication eight bus
cleaning cycles are run through, i.e. stop sequences
are sent in order to reset a possibly remaining slave.
Pin ADR1 Pin ADR0 EEPROM Address Range
lo
lo
iC-MV 1: 0x00 - 0x03
lo
hi
iC-MV 2: 0x04 - 0x07
hi
lo
iC-MV 3: 0x08 - 0x0B
hi
hi
iC-MV 4: 0x0C - 0x0F
Table 17: Address Range
Depending on the address, each iC-MV has a different
address range for its configuration. At address 0xF, the
CRC checksum (polynomial 0x11D / start value = 1) is
valid for the entire 15 bytes. Each iC-MV checks this
CRC byte. In case of an error, the reading process is
restarted. Pin SLO provided by the SSI interface and
pin NERR are at a high level until a successful startup
(CRC check OK) is reached. The data at address 0x03,
0x07 and 0x0B is not used.
Devices and Addressing
Number of iC-MV 1
iC-MV 1
0b00
iC-MV 2
iC-MV 3
iC-MV 4
2
0b01
3
0b10
4
0b11
Table 18: Address Allocation
SERIAL INTERFACE (SSI)
SCLK
SLI
SLO
MSB
LSB
MSB
LSB
MSB
LSB
MSB
MV1
LSB
ERROR
MV4
ERROR
iC-MV4 DATA
iC-MV3 DATA
iC-MV2 DATA
iC-MV1 DATA
Figure 14: SSI protocol
ERROR BITS
Two to four iC-MV devices are serially cascaded with
their SLI and SLO ports and are each connected with
the clock, SCLK. During an SSI transmission, iC-MV 1’s
position data is transferred to iC-MV 2 and so on up until
the master. This is illustrated in Figure 9. Each iC-MV
synchronizes its position data to the predecessor and
sends them to the next device. The SSI master thus
receives internally synchronized multiturn data. The
number of data bits to be transmitted is determined by
the data length DL(2:0). During synchronization the
MSB of the preceding iC-MV is compared to the own
synchronization bit and the position value is corrected
by one, if necessary. This requires the iC-MV’s offset
register to be programmed correctly.