IC-MV Datasheet, PDF (20/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
SYNCHRONIZATION
preliminary
Rev B1, Page 20/28
Calculation example for a gear reduction of 1:16
Step 1: Set configuration offset calculation
SYNC = 0x0
OFFSET = 0x00
DL = 0x07 (8-bit data length)
HIDATA = bit 7 to 4 of previous iC-MV (or initial singleturn device) position data
LODATA = bit 3 to 0 of following iC-MV position data (refer to Figure 9)
Step 2: Read position data and calculate offset
Offset calculation for ratio 1:16
OFFSET x
HIDATA x (4 bits)
LODATA (4 bits)
OFFSET 1 = singleturn HIDATA - iC-MV 1 LODATA
OFFSET 2 = iC-MV 1 HIDATA 1 - iC-MV 2 LODATA
OFFSET 3 = iC-MV 2 HIDATA 2 - iC-MV 3 LODATA
OFFSET 4 = iC-MV 3 HIDATA 3 - iC-MV 4 LODATA
90 ° reserve
+4
+4
+4
+4
calc. of next HIDATA x
pos. MV 1 + OFFSET 1
pos. MV 2 + OFFSET 2
pos. MV 3 + OFFSET 3
pos. MV 4 + OFFSET 4
Table 19: Offset Calculation for Ratio 1:16
Note:
The sequence described above must be followed for the calculation. The calculated offset correction is
essential to allow a successful synchronization.
Step 3: Set configuration for ratio 1:16
SYNC = 0x1
OFFSET = Calculation with offset positions from Table 6
DL = 0x03 (4-bit data length)
Synchronization Monitoring
If the bit ERRSY is activated, the synchronized position data is checked for consistency. The error is displayed via
the error bit in the SSI protocol, if configured. Synchronization monitoring only works with DL = 0x03.