IC-MV Datasheet, PDF (24/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
preliminary
iC-MU with 3 iC-MVs
VDD
EEPROM
SDA
SCL
SDA
SCL
MTC
MTD
VPA
VPD
iC-MU
MASTER TRACK
PORT A
PA0
PA1
B
PA2
NONIUS TRACK
PA3
Serial Interface
B
PORT B
I2C
PB0
Hall sensors
PB1
Configuration
RAM
128 Byte
PB2
PB3
ANA/DIG Output
MTI
VNA
VND
Rev B1, Page 24/28
VDD
GND
Supply
NPRES
MA
SLI
SLO
BiSS
Interface
A
B
Incrementalout+
Z
NERR Output
NERR
VDD
ERROR
VDD
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 3
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
VDD
VDD
EEPROM
SDA
SCL
VDD
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 2
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
GND
EEPROM INTERFACE
SCL SDA ADR0 ADR1
VDD
VDD
NERR
SLO
8 BIT
VDD
B
PCOS
B
PSIN
CONVERSION
LOGIC
B
NSIN
B
NCOS
SIN/DIG
HALL SENSOR
iC-MV 1
SERIAL INTERFACE
QD QD QD QD QD
SLI
SCLK
EEPROM INTERFACE
GND SCL SDA ADR0 ADR1
SDA
SCL
Configuration
Interface
Figure 20: iC-MU with 3 iC-MVs