IC-MV Datasheet, PDF (4/28 Pages) IC-Haus GmbH – 8-BIT HALL ENCODER

iC-MV 8-BIT HALL ENCODER WITH
CASCADABLE SERIAL INTERFACE
PACKAGING INFORMATION
preliminary
Rev B1, Page 4/28
PIN CONFIGURATION
QFN16 (3 mm x 3 mm)
16 15 14 13
1
12
2
<P-CODE>
11
3
<P-CODE>
10
4
<A-CODE>
9
5678
PIN FUNCTIONS
No. Name Function
1 n.c.¹⁾
2 VDD +4.5 V to +5.5 V Supply Voltage
3 NERR Open Drain Error Output
(NOSBY = 0x1),
Standby Input (NOSBY = 0x0),
Analog Output GAIN and NCOS
4 n.c.¹⁾
5 ADR1 Address Pin 1 (active hi),
Analog Input VTC (MODE)
6 ADR0 Address Pin 0 (active hi),
Analog Input VTS (MODE)
7 n.c.¹⁾
8 GND Ground
9 n.c.¹⁾
10 SDA EEPROM Interface, I²C Data Line
11 SCL EEPROM Interface, I²C Clock Line
12 n.c.¹⁾
13 SLO Serial Data Output (SSI),
Analog Output PCOS (Analog Out),
Threshold Output STOUT,
Clock Output CLK (Digital Test),
Incremental Output Z (ABZ Operation)
14 n.c.¹⁾
15 SLI Serial Data Input (SSI),
Analog Output NSIN (Analog Out)
and VREF (Digital Test),
Incremental Output A (ABZ Operation)
16 SCLK Serial Clock Input (SSI),
Analog Output PSIN (Analog Out)
and Analog Output GAIN (Digital Test),
Incremental Output B (ABZ Operation)
BP Backside Paddle ²⁾
IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes);
1) Pin numbers marked n.c. are not connected.
2) Connecting the backside paddle is recommended by a single link to GND. A current flow across the paddle is not permissible.