HY5S7B6LF-H Datasheet, PDF (6/51 Pages) Hynix Semiconductor – 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

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512Mbit (32Mx16bit) Mobile SDR Memory
HY5S7B6LF(P) Series
BALL DESCRIPTION
Ball Out
F2
SYMBOL
CLK
F3
CKE
G9
CS
G7,G8
BA0, BA1
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9,
G2, G1
A0 ~ A12
F8, F7, F9
RAS, CAS, WE
F1, E8
UDQM, LDQM
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1, A2
DQ0 ~ DQ15
A9, E7, J9 /
A1, E3, J1
VDD / VSS
A7, B3, C7, D3
/ A3, B7, C3,
D7
VDDQ / VSSQ
E2
NC
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among (deep) power down, suspend or
self refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and
LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask : Controls output buffers in read mode and masks input data
in write mode
Data Input/Output : Multiplexed data input/output pin
Power supply for internal circuits
Power supply for output buffers
No connection
Rev 1.0 / Jan. 2007
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