HY5S7B6LF-H Datasheet, PDF (12/51 Pages) Hynix Semiconductor – 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

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512Mbit (32Mx16bit) Mobile SDR Memory
HY5S7B6LF(P) Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
RAS Cycle Time
RAS to CAS Delay
RAS Active Time
RAS Precharge Time
RAS to RAS Bank Active Delay
AUTO REFRESH Period
CAS to CAS Delay
Write Command to Data-In Delay
Data-in to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
DQM to Data-In Mask
MRS to New Command
Precharge to Data Output
High-Z
CAS Latency=3
CAS Latency=2
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
Symbol
tRC
tRCD
tRAS
tRP
tRRD
tRFC
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
tDPE
tXSR
tREF
H
Min Max
S
Min Max
Unit
Note
72.5 -
90
-
ns
22.5 - 28.5 -
ns
50 100K 60 100K ns
22.5 - 28.5 -
ns
15
-
19
-
ns
80
-
80
-
ns
1
-
1
- CLK
0
-
0
- CLK
2
-
2
- CLK
tDPL+tRP
2
-
2
- CLK
0
-
0
- CLK
2
-
2
- CLK
3
-
3
- CLK
2
-
2
- CLK
1
-
1
- CLK
120 - 120 -
ns
-
64
-
64 ms
Rev 1.0 / Jan. 2007
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