HY5S7B6LF-H Datasheet, PDF (23/51 Pages) Hynix Semiconductor – 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

11
512Mbit (32Mx16bit) Mobile SDR Memory
HY5S7B6LF(P) Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)
Current
State
CKE
Command
Previ-
ous Cy-
cle
Current
Cycle
CS
RAS
CAS
WE
BA0, Amax
BA1 -A0
Action
Notes
H
H
H
X
X
X
H
H
LH XX
H
H
L
L
H
X
3
Refer to the idle State section
of the Current State
3
Truth Table
3
H
H
L
L
LHX
X Auto Refresh
H
All
Banks
H
Idle
H
H
H
L
L
L
L
OP CODE Mode Register Set
4
L
H
X
X
X
L
LH XX
L
L
L
H
X
3
Refer to the idle State section
of the Current State
3
Truth Table
3
H
L
L
L
LHX
X Entry Self Refresh
4
H
L
L
L
L
L
OP CODE Mode Register Set
L
X
X
X
X
X
X
X Power Down
4
H
Any State
other than
H
listed
above
L
Refer to operations of
H
X
X
X
X
X
X the Current State
Truth Table
L
X
X
X
X
X
X
Begin Clock Suspend
next cycle
H
X
X
X
X
X
X
Exit Clock Suspend
next cycle
L
L
X
X
X
X
X
X Maintain Clock Suspend
Note :
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered
from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high and is maintained for a minimum 200usec.
Rev 1.0 / Jan. 2007
23