HY5S7B6LF-H Datasheet, PDF (4/51 Pages) Hynix Semiconductor – 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

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512Mbit (32Mx16bit) Mobile SDR Memory
HY5S7B6LF(P) Series
FEATURES
● Standard SDRAM Protocol
● Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
● MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Programmable burst length: 1, 2, 4, 8 or full page
● Programmable Burst Type : sequential or interleaved
● Programmable CAS latency of 3 or 2
● Programmable Drive Strength
● Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
● -25^oC ~ 85^oC Operation Temperature
- Extended Temp. : -25^oC ~ 85^oC
● Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead), 10 x 13 [mm²], t=0.1mm max
HY5S7B6LFP : Lead Free
HY5S7B6LF : Leaded
512M SDRAM ORDERING INFORMATION
Part Number
HY5S7B6LF-H
HY5S7B6LF-S
HY5S7B6LFP-H
HY5S7B6LFP-S
Clock Frequency
133MHz
105MHz
133MHz
105MHz
CAS
Latency
3
3
3
3
Organization
4banks x 8Mb x 16
Interface
54Ball
FBGA
LVCMOS
Leaded
Lead Free
Rev 1.0 / Jan. 2007
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